Nvidia ASIC Physical Design Engineer - New College Grad 

China, Shanghai 

225720395

What you'll be doing:

• Chip integration and netlist generation

• Synthesis, RTL/netlist quality check, Formal Verification

• Constraints creation and validation, timing budget.

• Work with ASIC team to analyze/resolve special timing issues.

• Cross-Team collaboration to implement chip partitioning and floorplan

• Work in conjunction with PR engineers to achieve timing closure

• Achieve special mode timing closure, such as io, test, clock, async etc.

• Function eco creation and method development

• Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)

• Methodology and flow automation development for above areas.

What we need to see:

• MS in EE or Microelectronics

• Project experience in IC design implementation

• Courses taken in circuit design, digital design

• Hand-on experience in EDA software from Synopsys(DC/FC/PT/Formality/ICC2),Cadence (Genus/LEC/Innovus) is helpful

• Proficient user of Python or TCL is helpful

• Proficient in English reading and writing