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Google ASIC Design Engineer Core IP United States, California, Mountain View 215920478
01.12.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience working with architecture, design, and implementation of digital logic using Chisel.
- Knowledge of accelerators (e.g., Machine Learning or GPUs) or similar high performance designs.
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