Nvidia Senior Design Verification Engineer 

China, Shanghai 

21054797

What you'll be doing:

• Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality products.

• Read the IAS and design specs to understand the design requirements and build a corresponding test plan. Review the testplan with arch/design engineers.

• You responses to build a block/IP testbench based on UVM methodology.

• The responsibilities include building a test run and a regression flow. Triage failures in regression and help the designer root cause the bug.

• Work includes building various metrics (passing rate, functional coverage, etc) and monitoring its health.

• Take SOC verification on full chip test environment for IPs

• Analyse functional/code coverage results and identify the coverage holes. Work with the design engineer to improve the coverage score.

• Deploy the advanced verification methodology and infrastructure of the SOC/IP

What we need to see:

• BS / MS in electrical / computer engineering or equivalent experience.

• 3+ years (MS) or 5+ years (BS) working experience.

• Familiar with advanced verification methodology, tools and flow

• Fully experienced verification flow, including testplan, test, coverage model, testbench, and BFM modeling.

• Deep understanding of Verilog and HVL (High-level Verification Language)

Ways to stand out from the crowd:

• Strong programming skills in Perl and C/C++is plus

• Having good architectural or design experience is a big plus.

• At least good at one of the scripting programming languages: Perl, Shell, Ruby, Python.