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What you'll be doing:
You will participate in the research of verification methodology to improve automation and productivity to produce Nvidia’s new high-quality products.
Read IAS and design specs to understand the design requirement and build corresponding testplan. Review the testplan with arch/design engineers.
You responses to build block/IP testbench based on UVM methodology.
The responsibilities include building test run and regression flow. Triage failures in regression and help designer root cause the bug.
Work includes Build various metrics (passing rate, functional coverage, etc) and monitor its health.
Take SOC verification on fullchip test environment for IPs
Analyse functional/code coverage result and identify the coverage holes. Work with design engineer to improve the coverage score.
Deploy the advanced verification methodology and infrastructure of the SOC/IP
What we need to see:
BS / MS in electrical / computer engineering or equivalent experience.
3+ years (MS) or 5+ years (BS) working experience.
Familiar with advance verification methodology, tools and flow
Fully experienced verification flow, including testplan, test, coverage model, testbench, BFM modeling.
Deep understanding in Verilog and HVL (High-level Verification Language)
Ways to stand out from the crowd:
Strong programming skills in Perl and C/C++is plus
Having good arch/design experience is big plus.
At least good at one of the script programing language: Perl, Shell, Ruby, Python.
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