Palo Alto Sr Cloud NW Security Engineer NGFW - Santa 

United States, California 

20507853

Being the cybersecurity partner of choice, protecting our digital way of life.

Your Career

As a Design engineer on the ASIC team, you will create complex digital logic for our groundbreaking next-generation firewall products that meet or exceed industry-leading requirements for features, performance, and reliability. You will define architecture and microarchitecture specifications, implement logic, and validate the designs on diverse platforms including simulation, emulation, formal verification, and silicon validation.

Your Impact

• Create design specifications and define the ASIC architecture and microarchitecture in close collaboration with the Systems Architecture team

• Implement RTL designs in SystemVerilog

• Ensure that designs meet aggressive goals for functionality, performance, and reliability in close collaboration with ASIC verification and systems validation engineers

  • Evaluate and enhance test plans to maximize coverage

  • Debug complex test scenarios

  • Analyze coverage reports and suggest new tests to close coverage gaps

  • Define and implement sophisticated design for debug mechanisms

• Ensure that designs meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical design engineers

  • Perform synthesis

  • Optimize floorplan

  • Analyze and reduce power consumption

  • Close timing

• Define new methodologies to continuously improve quality and velocity

• Create powerful scripts to automate design tasks

Your Experience

• BS in EE, CE, or CS required - MSEE preferred or equivalent military experience required

• Minimum 8 years experience in ASIC design

• Demonstrated success in taking multiple ASIC products from concept to mass production

• Expertise in SystemVerilog for design

• Technical strength in the following areas is required:

  • Defining microarchitecture to optimize power, performance, and area

  • Lint, CDC, RDC, and X verification

  • Debugging simulation, emulation, and silicon validation

  • Analyzing physical design reports and fixing timing and power violations

  • Analyzing code coverage results

• Experience in the following areas is a plus:

  • Networking and cyber security

  • Working knowledge of PCIe or Ethernet standards

  • Experience with hardware implementation of Search Algorithms

  • Formal property verification

  • Silicon validation - bringup, test, debug, and regression

  • Creating models in Python and C/C++

  • Synthesis, equivalency check, and automatic formal verification

• Skilled in writing powerful, modular, and scalable scripts in Python and UNIX shell to automate design tasks

• Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status

• Strong leadership, collaboration, and communication skills

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $148,000 - $180,000/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found .

All your information will be kept confidential according to EEO guidelines.