Nvidia VLSI Timing Methodology Intern - Summer 

United States, California 

198879026

What You'll Be Doing:

• Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
• Work on various aspects of STA, constraints, timing and power optimization.

What We Need to See:

• Pursuing BS or MS in Electrical or Computer Engineering.
• Understanding of CMOS circuit design in FinFET technology and mathematics/physics fundamentals of electrical design.
• Experience with 3DIC design flows and related technologies.
• Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS), CDC, signal/power integrity, etc.
• Understanding crosstalk, electro-migration, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.
• Experience with coding - TCL, Python – and familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.

You will also be eligible for Intern

Applications for this job will be accepted at least until November 16,2025.