Nvidia Senior VLSI CAD Engineer Timing Methodology 

United States, California 

68123819

What you’ll be doing:

• Develop robust flows in Python linking PrimeTime, Innovus/ICC2, SeaHawk, and other EDA tools with internal optimization tools for timing, power, and IR drop

• Work with designers to craft strategies for unusual timing problems that arise in multivoltage paths, pad rings, replicated hierarchy, latch loops, clock domain crossing, etc.

• Deploy graph-based databases suitable for LLMs and other AI-based flow tools

• Help navigate the transition from Perl/TCL/Make based flows to Python.

• Guide new designers to efficiently use tools and help lead future tool development.

• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

• BS or MS in Electrical Engineering (or equivalent experience)

• 6+ years experience in VLSI timing closure with some mix of both CAD and design experience.

• Advanced experience in timing closure, including significant experience with PrimeTime

• Fluency in Python

• Familiarity with Perl, TCL, and Make

• Experience in using AI-coding assistants such as Cursor

• Strong communication and interpersonal skills

Ways to stand out from the crowd:

• Experience with graph databases, especially in use as knowledge graphs for LLMs or GNNs.

• Familiarity with algorithms used for timing, power, and IR drop optimization

• Experience with place & route tools, such as Innovus or ICC2

• Fluency in C++