Qualcomm Implementation Timing / STA Design Engineer 

United States, California, San Diego 

198601460

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Job Description: Principal Duties and Responsibilities

• Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.

• Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.

• Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.

• Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.

• Analyze timing across modes and corners, understand concepts like path pessimism and margins.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$134,500.00 - $201,500.00