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In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII.
Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design.
Static timing analysis.
Power Optimization.
Design Convergence Experience at IP, SoC level.
Ability to work in a highly dynamic environment across geographies.
Back end design and implementation of new features.
Post silicon performance push activities.PPA improvement and Methodology improvements
Qualifications:These jobs might be a good fit