In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence
In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence .The position is relevant for both Herzliya/ Haifa site
Excellent graduates from leading universities
Highly motivated
Analytical thinking
student for B.Sc. in Computer Science and Math or Computer Science and Physics only with 2 semester remaining studies