In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence .The position is relevant for both Herzliya/ Haifa site
Key Qualifications
Excellent graduates from leading universities
Analytical thinking
Highly motivated
Education & Experience
B.Sc. in Computer Science and Math, Computer Engineering, Computer Science and PhysicsM.Sc/PhD Mathematics