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What You'll Do
Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in design, verification, physical design, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.
Responsibilities
Architectural work: in-depth understanding of the architecture, and identification of problems and solutions.
All aspects of implementation: specification, design, verification, timing-closure, power-optimization, and flow automation.
Physical design work: timing path analysis, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
Document and improve standard methodologies to make product successful.
Who You Are
Worked in architecture and definition of high-scale, high-performance ASICs.
Validated experience in implementation: specification, design, verification, formal verification, system testing.
Validated experience in physical design aspects: timing analysis and closure, power/area optimizations, macro size/placement analysis.
Validated experience in high bandwidth memory subsystems and timing closure.
5+ years of hands on experience in large-scale, high-performance ASIC.
BS/MS in EE/CS.
Minimum Qualifications
End-to-end design experience from Verilog to gates, block planning, area/timing closure is helpful.
RTL development and verification (VCS, System Verilog, UVM/OVM, Formal verification)
Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS.
Gate-level understanding of RTL and Synthesis
Programming/scripting skills (C, C++, Perl)
Hardware Emulation Platforms and tools (such as EVE, Veloce)
5+ years of substantial experience
Good written/verbal interpersonal skills and leadership skills.
Who You'll Work With
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