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What you will be doing:
Partner with system architects to understand the functional and performance requirements of a unit or feature
Define micro-architecture and develop RTL for owned unit and/or feature
Work with verification and physical design team to ensure that the unit or feature is accurately verified and implemented
You will own silicon bring-up in conjunction with post silicon validation and SW teams
Mentor junior engineers and guide them in their work
What we need to see:
BS / MS with 2+ years of relevant experience
Strong digital design experience
Experience in design of complex features or units
Background in RTL coding using Verilog or System Verilog
Experience in using design and verification tools (Synthesis, lint, simulation tools)
Knowledge of industry specifications like CHI/AXI/ACE
Experience in memory management unit, interconnect design or cache controller design desirable
Good debugging and problem solving skills. Scripting knowledge
Good interpersonal skills and ability & desire to work as a team
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