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is uniquely positionedto have an end-to-end view of the product development cycle - from early arch definition through bringup to product release. Our ArchDev arm is a hub for all silicon and system-level feature development, tradeoff analysis, system integration solutions, andPOR alignment.
What you'll be doing:
Innovate and Design:Architect, design, and integrate system-level clocks management policies, controllers, and features to address high perf, low power product needs.
Collaborate and Lead:Collaborate with system architecture, power architecture, ASIC, SW/FW, validation, and production teams throughout the product life cycle; Lead system-level clock architecture, design, productization, debugging, and deployment.
Push the Boundary:Define roadmaps by tracking industry/market trends, collecting current product feedback, prototyping innovations, and conducting data-driven tradeoff analysis.
Hands-on Actions:
What we need to see:
BS or MS in Electrical/Computer Engineering or equivalent experience.
8+ years in ASIC, clock design/architecture, silicon system design, and debugging.
Strong fundamentals in digital design, clock design, low power design, DVFS, noise, timing, control systems, micro-architecture, and power architecture; Deep understanding of SW/FW and HW/SW interaction; Helpful to have prior experience related to clocks, PLL, and VCO design, characterization, validation, bringup, and debug.
Hands-on lab experience (oscilloscopes, multimeters, logic analyzers) is a plus.
Basic programming and scripting skills such as C/C++, Python, Perl
Excellent problem-solving, teamwork, and interpersonal skills.
You will also be eligible for equity and .
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