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Nvidia Senior Memory Post Silicon Qualification Engineer United States, California 154987942
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Bring up a high-speed memory interface on complex chips like GPUs and SoCs.
Functional validation, IO tuning, and PVT testing of the memory controller and DRAM have paved the way for successful silicon productization.
Optimizing Memory IO settings to support multiple memory configurations involving different types of DRAMs and vendors.
Identify any functional issues, perform root-cause analysis, and drive closure of the issues found. Coordinate with design, arch, and board teams, where required.
Collaborate with the pre-Si team to understand the new features and create appropriate validation test plans.
B. Tech or M. Tech in Electronics Engineering or equivalent experience
8+ years of experience in the semiconductor industry with a minimum of 2 years in memory interface validation.
Strong understanding of the protocol for DRAM types like GDDR/LPDDR
Familiarity with HW lab environment and understanding of lab equipment like DMM, Oscilloscope, thermal solutions, etc.
Background in understanding PCB stack-up, board layouts, power planes, and SI guidelines.
Experience in writing lab automation scripts using C/Python/Perl.
A strong standout colleague; self-motivated with great interpersonal skills.
You will also be eligible for equity and .
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