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What you’ll be doing:
Develop and Qualify system level DFT features on our GPU's and SOC's. Prototype DFT features on silicon, analyze return on investment, create/maintain feature bring-up plans , maintain schedule and alignment across various teams.
Lead debug efforts from HW side to root cause feature sequence bugs, silicon bugs and complex system level issues caused by interactions between multiple HW and SW features.
Craft creative solutions and WARs through lab experimentation and effective use of debug tools, to achieve high product quality at speed of light schedules.
Support manufacturing and customer facing teams to expertly address production needs and issues on the relevant features.
Work closely and proactively with other engineering teams such as DFT design team, system architects, chip and board designers, software/firmware engineers, HW/SW QA teams and Applications engineering teams to drive design, development, debug and release of next generations products.
What we need to see:
BS or MS degree in Electrical or Computer engineering or equivalent experience.
12+ years of proven experience with system level post silicon bring-up and debug.
Experience in Silicon DFT bring up/validation. Experience in optimizing quality of silicon vs other trade offs like cost.
Strong EE fundamentals, knowledgeable in DFT, digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.
Deep understanding of firmware/driver structures and their interaction with hardware.
Working knowledge of PVT dependencies and binning methodologies.
Knowledgeable in performance and power management techniques such as DVFS, clock and power gating, clock sequencing, binning, and power throttling.
Hands-on validation experience with lab debug and tools (oscilloscopes, multimeters, logic analyzers).
Effective in a collaborative environment.
Excellent problem solving, teamwork, and interpersonal skills.
Crowd:
DFT experience specifically in system test features for in field test.
Bringup experience with GPU/SOC architecture is a plus.
Past experience as a Silicon Bring up Lead.
Experience of succeeding in a highly matrix organization.
Driven process/methodology improvements.
You will also be eligible for equity and .
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