Responsibilities:- Quantify power and analyze vector traffic for design coverage
- Identify design opportunities to optimize power
- Ensure delivered IP can achieve partner goals.
- Support team flexibility by keeping up to date with their latest issues & challenges.
Required Skills and Experience :- Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering or other relevant technical fields.
- Outstanding knowledge of system power analysis & optimization
- Significant experience in & knowledge of the entire IC design flow, from RTL through to GDS2 across multiple process nodes down to 3nm.
- Low power design techniques (power gating, voltage/frequency scaling)
- The ability to communicate insights effectively to engineers both with & without an implementation background.
- Able to identify and solve emerging challenges, develop associated tooling & methodologies & promote their use with international teams.
- Solid scripting skills eg. TCL, Python, Perl, R.
“Nice To Have” Skills and Experience :- Ownership of the technical delivery for a large project or program.
- Knowledge around Arm based SoCs.
- Verilog RTL design.
- Experience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, CSS, PHP, SQL, Perl, Python, Ruby, Svelte, …
- Experience in static & dynamic IR-drop analysis.
In Return:A place in a welcoming team with competitive pay & benefits. This includes a 4-week sabbatical every four years atop of the standard 4 to 5 weeks holiday & national holidays.
Salary Range:$221,127-$299,172 per year