Nvidia Senior Package Layout Engineer 

Taiwan, Taiwan Province, Hsinchu 

146498972

What you'll be doing:

• As part of a Package Layout team, you will collaborate to implement high speed and PDN design for ASIC packages.

• Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using APD or SiP tools.

• Optimize package pin out incorporating system level trade-offs of pins assignment.

• Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.

• In close co-operation with the SI/PI/HW design teams and product teams

• Planning, ensuring stakeholder management and leading projects from start to finish

What we need to see:

• B.Sc. Electrical Engineering or any equivalent experience.

• Minimum of 5+ years hand-on in Package or/and PCB Layout; including high speed design signal integrity practice; PDN designing and planning

• Experience in substrate layout of wire bond and flip chip packages, preferred

• Knowledge in substrates or board manufacturing process

• Significant background with APD or SiP and/or other PCB layout tools

• English communication skills (written and verbal) are required for this role

Ways to stand out from the crowd:

• Knowledge in Ansys (SIwave, HFSS) or Cadence (Sigrity, PowerSI) simulation tools

• Familiarity with Skill language (Cadence) and basic parsing abilities(Python/Perl/Shell-scripting)