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Responsibilities include, but are not limited to the following:
High-level architecture specification analysis – interactive authoring and review.
Micro-architecture development and documentation.
High-quality, high-performanceVerilog/SystemVerilogRTL implementation based on a design specification – may also include areas such as asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations and pipelining, multi-threaded designs, and integrating third-party IP.
Converging the design to timing closure by RTL optimization strategies.
Superb RTL debugging skills with well thought out robust RTL solutions.
Working with cross functional teams such as Verification Engineering, Software/Firmware Engineering and Validation Engineering to support any issues that may arise on the RTL design.
Lab support for silicon as it progresses through validation.
Must work in person at the site
Desired attributes, but not required:
PCIe protocol
CXL protocol
AMBA protocols
Education and Experience Requirements:
Bachelor’s degree required in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or equivalent Engineering degree.
8+ years of relevant industry experience
Compensation and Benefits
The annual base salary range for this position is $91,200 - $152,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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