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Apple AMS Design Verification Engineer m/f/d Germany, Bavaria, Munich 111510827
01.06.2024
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Description
Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design.
Key Qualifications
- Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
- Hands-on experience with constrained random verification environments
- Hands-on experience with Assertion Based Verification
- Basic design background in support of verification results analysis
- Knowledge of Object Oriented Programming (OOP)
- Familiarity with system design using C (C++) or Verilog is a plus
- ATE functional test pattern generation for logic testers is a plus
- Proficiency in English language is required
Education & Experience
MSc in Electrical Engineering or industrial experience equivalent.
Additional Requirements
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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