- Work with systems team to understand the top level requirements of the digital functions and develop detailed specifications - Implement the function in Verilog RTL to specification - Partition the function between HW and FW for most efficient implementation - Develop RTL and FW to implement the function - Perform unit level testing on the RTL function Other responsibilities could include: - RTL synthesis - Equivalence checking Static Timing Analysis - Develop FW to support DV and ATE environments - Support the DV team by writing self-checking tests as required