Nvidia Senior Physical Design Timing Engineer - Hardware 

United States, Texas 

110862640

What you'll be doing:

• Drive physical design and timing of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level.

• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

• Work in a cross-functional environment interacting with multiple teams.

• Apply knowledge and experience to improve the convergence flows working with the Methodology Team.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 2+ years experience in Synthesis and Timing

• Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• Hands on experience in logic synthesis and equivalence checking/FV required. Good understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.

• Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.

• Understanding of DFT logic and hands-on experience in design closure.

• Expertise in analyzing and converging crosstalk delay, noise glitch, andelectrical/manufacturingrules in deep-sub micron processes.

• Knowledge in process variation effect modeling and experience in design convergence taking into account variations.

• Experience in critical path planning and crafting needed.

• Expertise and in-depth knowledge of industry standard EDA tools.

• Proficiency in programming and scripting languages, such as, Perl, Tcl, Make, Python, etc.

Ways to stand out from the crowd:

• Background in high-performance design, such as CPU, implementation and timing convergence, this is a plus

• Experience with DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.

• Knowledge in circuits, SPICE simulations, and/or transistor level STA.

• Experience in methodology and/or flowdevelopment/automation.