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Apple ASIC Design Engineer - Memory Cache Controller United States, California 108847023
02.05.2024
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Key Qualifications
- Development of memory systems.
- Experience in RTL/micro-architecture definition.
- Experience in PPA (performance/power/area) analysis.
- Knowledge of dedication coherent memory system or interconnect architectures.
- Strong cache design background including good understanding of different memory organizations and tradeoffs.
- Knowledge of dedication memory subsystem and dram controller.
- Hands on Experience with multi-processor cache coherence protocols
Description
Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis.Develop/debug RTL design of different sections of the cache.
Education & Experience
Bachelors Degree + 0 Years of Experience.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $55.82 and $84.09/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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