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Intel Physical Design Engineer United States, Texas 106957213
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Key Responsibilities:
- Lead physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
- Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
- Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
- Analyzes results and makes recommendations to fix violations for current and future product architecture.
- Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
- Optimizes design to improve product level parameters such as power, frequency, and area.
- Participates in the development and improvement of physical design methodologies and flow automation.
The candidate should exhibit the following:
- Excellent problem solving and communication skills
Minimum Qualifications:
The candidate must have a Bachelor's Degree in Electrical/Computer Engineering, Computer Science, or related major with 10+ years' experience -OR- a Master's Degree in Electrical/Computer Engineering, Computer Science, or related major with 8+ years' experience with:
- Block/Top Floor planning , Synthesis and Place and Route, STA (preferably in complex Mixed-Signal blocks involving multiple analog blocks)
- Technical lead for RTL2GDS at block/top level OR STA lead of block/top level
- Industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.)
- Scripting languages (eg. TCL, Perl, Python etc.)
Preferred Qualifications:
- 8+ years of experience in Physical Design
- Synthesis and PNR flows on Multi-Voltage/Low Power designs with greater than 1M instances
- Good understanding of low power rule verification, Clock distribution schemes, Timing constraint analysis and feedback to Front-End teams, Static Timing analysis, Timing ECO Generation at block/top level.
- Handson experience in scripting using EDA tool API interface for Cadence or Synopsys
- Prior experience in being a technical lead for junior engineers driving Synthesis/Place and Route or STA or Physical Verification or Electrical Verification tasks
- Excellent Scripting skills in Perl or Python
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.
Position of Trust
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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