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United States, Oregon, Asic Design Engineer jobs

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6,031 jobs found
19.05.2024
F

Forter General Application United States United States

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Description:
Competitive salary. Matching 401K Plan. Comprehensive and generous health insurance, including vision and dental coverage. Stock options. Generous paid parental leave options. Home office allowance. Cell Phone/Wifi reimbursement. Flexible PTO...
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31.05.2024
A

Apple ASIC Design Engineer United States, California, Cupertino

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Description:
Extensive Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog. Proficiency in front end tools and methodologies. Experience writing specifications and converting them to design....
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21.05.2024
A

Amazon Fall Applied Science Internship - United States Masters Stud... United States, Washington, Seattle

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Description:
Enrolled in a Master’s degree or equivalent in computer science, machine learning, engineering, or related fields. Experience in designing experiments and statistical analysis of results. Experience in understanding and ability...
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19.05.2024
A

Amazon Fall Applied Science Internship - United States PhD Student United States, Washington, Seattle

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Description:
Enrolled in a Ph.D. or equivalent in computer science, machine learning, engineering, or related fields. Experience in designing experiments and statistical analysis of results. Experience in understanding and ability to...
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24.05.2024
D

Dell Account Manager Client Executive - Cyber SaaS Northeast Unit... United States, Pennsylvania

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Description:
Assigned to specific Secureworks accounts that requires global execution and has the highest complexity and strategic importance to Secureworks. Ability to identify and validate customer priorities, business drivers, and outcomes....
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31.05.2024
A

Apple ASIC Design Engineer United States, California, Cupertino

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Description:
Proven track-record in digital design including RTL design experience. Strong understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate...
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21.05.2024
C

Cisco ASIC Design Engineer United States, California, San Jose

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Description:
You will author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology /...
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