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Soc Rtl Design - Memory Team jobs at Samsung in India, Bengaluru
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India
Bengaluru
13 jobs found
20.08.2025
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Samsung DFT Design Engineer - Foundry Team India, Karnataka, Bengaluru
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Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes. MBIST architecture planning,...
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20.08.2025
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Samsung SRAM Design Engineer - yrs India, Karnataka, Bengaluru
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Design highly competetive circuits to meet peroformance/power specificiations requested by customers. Guide and lead a group of engineers to deliver the SRAM IP in the given timelines. Analyse circuits and...
08.05.2025
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Samsung DRAM Verification - Memory Team India, Karnataka, Bengaluru
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Create new and improve existing verification environment. Apply Universal VerificationMethodology (SystemVerilog/UVM)and define verification plan as well as setup verification metrics in digital environments. Execute tests in these environments on RTL...
08.05.2025
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Samsung SoC RTL Design / SOC Integration - Memory Team India, Karnataka, Bengaluru
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10 to 15 years of work experience in VLSI SoC RTL design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock/reset, SoC...
07.05.2025
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Samsung Senior Staff Analog Design India, Karnataka, Bengaluru
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Senior Analog deisgner with relevent experience of 5 12 years in Analog and Mixed Signal Design.At least Full IP design experince in one of domains as listed below.Role and Low...
07.05.2025
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Samsung Physical Design Engineer - Foundry Team India, Karnataka, Bengaluru
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Hands on experience doing physical design and timing closure of complex blocks and full-chip designs. Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning,...
07.05.2025
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Samsung Physical Design - SOC / GPU India, Karnataka, Bengaluru
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Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA ,...
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Description:Full job details
Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes. MBIST architecture planning,...
These jobs might be a good fit
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