Samsung DFT Design Engineer -Memory Team 

India, Karnataka, Bengaluru 

953138548

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

• Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies
• Executed scan & MBIST insertion, ATPG and verification at full chip level
• Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts
• Generate, review and validate DFT constraints to achieve timing closure of high speed design
• Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)
  Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification
  Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests
• Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved
• Understanding of PowerEstimation/Managementfor DFT modes is preferred
• Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
• Strong written and oral communication skills

Qualifications