Rtl Micro-architecture Design Engineer Dram Controller_tb5-tb7_dram_memory jobs at Samsung in India, Bengaluru

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas:

• Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes
• MBIST architecture planning, repair architectures, insertion, verification
• Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs
• Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team
• Timing GLS, debug of fails in simulations
• Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures
• Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable
• Understanding of functional test cases, IO testing, testing of ARM processor cores

Qualifications

Role and Responsibilities

• Design highly competetive circuits to meet peroformance/power specificiations requested by customers
• Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
• Analyse circuits and indentify potential robustness gaps and find solutions to improve robustness of the design.

• Own the responsibility from SPEC to GDS and DK delivery.
• Review circuits, robustness reports and identify potential robustness issues.
• Review Layouts and suggest improvement areas to achieve competitive PPA
• Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
• Must be able to communicate effectively across different teams.

Skills and Qualifications

• Master/Bachelor in electronics
• Working experience (10+years) in preferably Memory design
• Understanding of RC network and finfet fundamentals are necessary.
• Custom or Compiler SRAM/ROM development experience
• Fundamentals of process variability and its effect on memory design
• Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)

• Stong understanding of circuit design fundamentals
• Critical path modeling concept, various type of models ( RC, C, Pai, ladder)
• Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitics etc
• Analysing layout and understanding of LLE effects.

• Bachelor's /Master degree in Computer Science,Electrical/ElectronicsEngineering, Engineering and 10+ years of experience in circuit design.

Role : Looking for Design verification Engineer with 3-5 years of experience

Responsibilities :

Good Understanding of UVM based Verification Methodology.

Develop IP level/System Level Testbench Components.

Able to develop Testplan, Checker plan and Coverage Plan based on Design Specification and requirements.

Develop Testcases , coverage bins and assertion based checkers .

Develop corner case scenario to cover the Coverage bins and achieve targeted functional coverage and code coverage.

Should be able create constrained random testcases for coverage of the design requirement.

Work closely with design engineers to achieve the Project Goal.

Take up responsibilities of complete verification of a design block.

Coordinating with other verification engineers for review and improve verification scope.

Should be able to debug any issues in the design.

Apply Verification best practises to optimize and improve overall verification.

Qualification :

Bachelors/Master Degree with 3-5 years of experience in design verification domain.

Expertise in SV,UVM and design verification methodologies.

Experience in EDA Tools , Good Hands on waveform viewer and coverage tools.

Experience in testplan , checker plan and coverage plan development.

Should be able to communicate technical details very effectively with both designers and peers.

Good Debugging and Analytical Skills.

Capability to understand DRAM JEDEC Specifications (DDR4/DDR5) and internal workings of Memory Controllers.

Understanding of next generation interconnects like PCIe Gen5, CXL is a plus.

Role : Looking for Design verification Engineer with 7+ years of experience

Responsibilities :

Architect and Develop IP level/System Level Testbench Environment using UVM.

· Employ UVM based Verification Methodology, assertions, functional/code coverage to reach verification goals.

Able to develop IP level/System Level Testplan, Checker plan and Coverage Plan based on Design Specification and requirements.

Develop assertion based checkers .

Work closely with design engineers to achieve the Project Goal.

Take up responsibilities of owning the complete verification of the IP.

Coordinating with other verification engineers for verification closure.

Should be able to support design teams in debugging any issues.

Should be able to mentor or train juniors in the overall process.

Apply Verification best practises and develop/enhance verification methodologies to optimize and improve overall verification.

Qualification :

Bachelor’s/Master’sDegree with 7-8 years of experience in design verification domain.

Capability to understand DRAM JEDEC Specifications (DDR4/DDR5) and internal workings of Memory Controllers.

Understanding of next generation interconnects like PCIe Gen5, CXL is highly desired.

Expertise in SV,UVM and design verification methodologies.

Proficiency in EDA Tools , Good Hands on waveform viewer and coverage tools.

Experience in testplan , checker plan and coverage plan development.

Should be able to communicate technical details very effectively with both designers and peers.

Good Debugging and Analytical Skills.

• Create new and improve existing verification environment
• Apply Universal VerificationMethodology (SystemVerilog/UVM)and define verification plan as well as setup verification metrics in digital environments
• Execute tests in these environments on RTL . Good debugging skills and Independent to work
• Closely cooperate with designers and team members.

DRAM Verification :

Requirement:

• Ideally 3-5 years of related work experience
• Good knowledge of SystemVerilog, Verilog
• Know-how of Unix programming languages such as Shell, TCL, Perl/Python etc
• Functional verificationexperience inUVM

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

• To Develop (System-Core/PowerManagement/Connectivity/Storage/Display / Ethernet/ IVI/HUD) Device drivers for ARM based Exynos Chipsets.
• Working knowledge of Linux / QNX device drivers
• Good knowledge of Linux kernel and device driver development
• Good experience with Bootloader, I2C, PMIC, UART, SPI, USB, UFS, MMC Power or similar device drivers.
• System level knowledge and experience in Board bring up and debugging.
• Good Knowledge of Debug tools and power and performance optimization.
• Good Knowledge of LinuxInternals/Frameworks/ARMArchitecture.
• Manage Samsung Exynos BSP / Device Driver Deliverables.
• Experience in Linux/Android BSP development at product level
• Knowledge on Linux/Android Power management framework Suspend/Resume.
• Knowledge on Runtime PM, CPU freq/Idle scaling governors, DVFS.
• Knowledge of ARM/CPU Architecture, cache and Linux scheduler is desirable.
• Ability to resolve system level power/performance issue during product development
• Experience in analyzing system level performance bottlenecks and fixing bench mark scores

Good to Have:

• To do the bring up of the latest Android Platform on these devices and product development with Latest Exynos SoCs.
• To involve in the development of the commercial phones with latest Android Releases and provide upgrades .
• To Provide customer support to different vendors who are making products with Exynos Family chipsets (Mobile/Wearables).
• Android HAL development Infotainment Media, Phone, Camera, BT, radio, Vehicle (anyone is fine)
• Good understanding of Android architecture and internals (AOSP, Binder IPC, HAL & Native services)
• Working on Android HAL layer and realizing various customer requirements on Android.

6 to 10 Years

Qualifications

Role and Responsibilities

• 10 to 15 years of work experience in VLSI SoC RTL design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, Flash Subsystem.

• Understanding of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.

• Creating micro-architecture and detailed design documents for SoC design keeping in mind performance, power, area requirements.

• Strong debugging skills and very good experience in DV tools like Verdi, NCSIM.

• SOC Integration experience preferred of Top Level, Block Level or Subsystem level.

• Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modelling team.

• Must have knowledge in clock domain crossing (CDC), Linting, UPF.

• Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc. is a must.

• Understanding and defining constraints and critical high speed path timing closure working with back end teams

Role and Responsibilities

- Low Jitter and high frequency PLL Design Experience . Both LC and Ring based PLL deisgn Experience

- General Purpose ADC and thermal Senors IP deisgn Experience

- High speed Serdes Design Experience.

- LDO , BGR and other Power managemnt blocks.

Skills and Qualifications

B.Tech/M.Tech / PHd

Role and Responsibilities

component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, StorageSolutions, AI/ML,5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

Roles and Responsibilities

Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs

• Hands on experience doing physical design and timing closure of complex blocks and full-chip designs.
• Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.
• Should have strong understanding of timing, power and area trade-offs and optimization of PPA.
• Power user of industry standard tools(ICC/DC/PT/VSLP/Redhawk/Calibre/Formality)and able to understand their capabilities.
• Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ .
• Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.
• Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).
• Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
• Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.
• Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
• Should have gone through recent successful SOC tape-outs.

Qualifications