Master Scheduler Npi Board System jobs at Nvidia

What You'll be Doing:

• Study and explore innovative techniques in bioinformatics, graph algorithms, machine learning, develop, deploy, and deliver brand-new computing software for a diverse array of bioinformatics applications used globally

• Perform detailed performance analysis and optimization to ensure optimal performance on current and next-generation GPU architectures.

• Collaborate with lighthouse clients and academic collaborators to understand their current and future challenges and provide outstanding HPC solutions.

• Collaborate closely with hardware engineering, CUDA engineering, and AI research groups to apply the latest technology to enable novel genomic analysis at scale.

What We Need to See:

• Bachelor's / Master's degree in Computer Science, a related technical field, or equivalent experience.

• 5+ years of experience n related field.

• Solid understanding of C/C++, CUDA, software design, and programming techniques.

• Experience with the design and implementation of sophisticated algorithms and data structures.

• Experience with GPU programming, debugging and performance tuning on NVIDIA GPUs.

• Knowledge and understanding of parallel programming, thread programming, concurrency control, memory management and scalability.

• Strong understanding of computer system architecture and operating systems.

Ways To Stand Out from the Crowd:

• Hands-on experience in using LLM, Graph Neural Network, Graph Transformer Network particularly those applied to genomics data.

• Strong collaborative and interpersonal skills to effectively guide and influence within a multifaceted, technical environment.

• Breaking a sophisticated problem to smaller modules that are fairly independent.

What you'll be doing:

• Define and drive architecture for complex, high-volume GPU products, ensuring they meet our ambitious performance and scalability goals.

• Perform and guide power and performance evaluation, trade-off assessments, and architectural modeling to identify optimal chip, package and system construction.

• Lead improvements in architecture, methodology and tools to improve the scalability of our system, collaborating closely with cross-functional engineering teams.

• Specify and optimize SoC subsystems such as memory architecture, test infrastructure and power management.

• Collaborate with RTL, verification, physical design, firmware, and software teams to successfully implement and integrate system components.

• Produce high-quality technical documentation of SoC architecture, specifications, and development trade-offs.

• Provide technical leadership and mentorship to junior architects and engineers, encouraging a culture of excellence and innovation.

What we need to see:

• Over 15 years in SoC architecture development or similar technical leadership roles.

• Proven track record of defining and delivering multiple high-volume SoC systems (such as CPU, GPU, modem, networking or similar).

• Proficiency in evaluating power/performance and architectural modeling in high-level programming languages.

• Strong understanding of SoC system fundamentals, including memory hierarchy, coherency, clocking, power domains, boot and reset, test, and debug methodologies.

• Hands-on experience with silicon bring-up, debug and tuning.

• Excellent interpersonal, leadership, and collaboration skills, with the ability to influence across organizations.

• Outstanding documentation, written, and verbal communication skills.

• Master's degree (or equivalent experience) in a relevant subject area: Computer Science, Electrical Engineering or Computer Engineering

Ways to stand out from the crowd:

• Experience with GPU or AI accelerator architecture, including platform aspects, off-chip I/O technologies, and networked multi-GPU systems

• Knowledgeable in modern packaging technologies, and their costs and benefits

• Knowledgeable in AI workload characteristics

• Outstanding analytical and problem-solving skills with a focus on optimizing performance, power, area, and complexity.

We need aSystem Fault Isolation Internwith expertise in physics, process andpackage technologies,

What you'll be doing:

• Gain experience in debugging product failures at the die, package, component, and board level

• Develop a working understanding of EFA and PFA techniques and tools including curvetracing, Electro-OpticalTerahertz Pulse Reflectometry (EOTPR), Vector Network Analyzer (VNA), Scanning Acoustic Microscopy (SAM), X-ray Computed Tomography (CT), Laser Voltage Probing (LVP),Optical/Electron/AtomicForce Microscopy, andUltra-thinning/delayeringand cross sectioning sample preparation techniques

• Build knowledge surrounding the interactions between process technology, physical design, and circuit design

• Develop innovations to help enhance the capability and efficiency of FA processes

What you need to have:

• Pursuing a Bachelors or Masters degree in Electrical/Computer Engineering, Chemical Engineering, Materials Science/Engineering, Physics, or other related field

• Lab experience with electrical and materials characterization tools

• Experience in one or more areas across silicon process technology, VLSI design, and FA tools such as Curve Tracer, SEM, Lock-in Thermography, Pulse Reflectometry, LVP, etc.

• Excellent communication skills and teamwork both cross-functionally and between companies

Ways to stand out from the crowd:

• Practical experience in silicon technology and/or design

• In-depth understanding of IC fabricationprocesses, electroniccircuit analysis, and semiconductor physics

• Hands-on experience with FA related analytical tools

• Ability to build, train, and maintain AI models

• Experience working with global teams

You will also be eligible for Intern

What you’ll be doing:

• Building and integrating tools to configure, simulate, and test robots

• Maintain and optimize the existing simulation stack for scalable robot and sensor simulation

• Integrate APIs to support large scale simulator deployments on distributed systems

• Develop microservices, using ZMQ, DDS, RPC, RESTful and other network level communication APIs

What we need to see:

• Pursuing or recently completed BS, MS, PhD (or equivalent experience) in Computer Science, Simulation, or related field

• Experience in systems software engineering

• Excellent C, C++, and Python programming skills

• Flexibility to adapt quickly to varying roles & responsibilities

• Experience with physics simulation, robotics or motion planning & controls

• Excellent interpersonal skills and ability to work optimally with multi-functional teams, principles, and architects across organizational boundaries and geographies

Ways to stand out from the crowd:

• Experience with Isaac Sim, Omniverse, USD, MJCF, URDF, CAD formats

• Background with physical robots, reinforcement learning, synthetic data generation

• Experience with UI/UX for user and developer facing tools

• Background with shipping and supporting software products

• Experience with system level optimization using multi-threading, asynchronous programming, concurrency and parallelism

What you'll be doing:

• Drive development and productization of NVIDIA’s DGX datacenter products and L11 systems.

• Lead debug efforts for L11 rack-level integration, creating and applying tools/scripts for failure identification and root cause analysis.

• Provide clear, actionable guidance to factories to resolve issues quickly and implement corrective actions that improve manufacturing quality and efficiency.

• Develop and document robust, stable recipes—including diagnostics, firmware, and software—for mass production ramp.

• Review and provide feedback on test plans and factory acceptance criteria, focusing on yield, quality, and efficiency.

• Collaborate with development, validation, and manufacturing test engineering teams to understand diagnostic and firmware release plans and their impact on system stability and quality.

• Influence test engineering and diagnostic teams to enhance test methodology, telemetry, and debug capabilities for precise FRU identification and isolation of firmware/test issues and to improve test coverage with the goal of preventing downstream escapes.

• Partner with product development teams to ensure designs are optimized for manufacturing.

• Present NPI status updates and critical issues to executive management.

What we need to see:

• Expertise in server platform architecture, CPU/GPU baseboards, and high-speed interfaces with proven system-level debug skills and exceptional diagnostic instincts.

• Strong knowledge of BMC, firmware architecture, and manufacturing diagnostics.

• Familiarity with L11 integration processes.

• Excellent communication skills to articulate problems and deliver clear recommendations.

• Strong analytical skills to synthesize complex information and provide actionable guidance.

• Leadership skills to manage factory operations and drive issue resolution.

• Collaborative mindset to work seamlessly with cross-functional teams and external partners.

• Results-driven approach to achieving optimal outcomes across all aspects of NPI operations.

• 12+ years in system engineering, debug, or equivalent relevant experience

• BS or higher in Electrical Engineering, Computer Engineering or equivalent experience

What you will be doing:

• Develop GPU architecture innovations and improvements, optimizing along the axes ofscalability/modularity,performance and power efficiency, area, yield, effort, and schedule.

• Benchmark GPU configurations (core count, memory and interconnect bandwidth) employing advanced packaging; identify optimal designs for future data center workloads.

• Develop and enhance architecture analysis infrastructure, including performance simulators, testbench components and analysis tools, to evaluate configurations under different constraints.

• Implement and maintain high-level functional and performance models. Analyze application workloads and performance simulation results to identify areas of architecture improvements.

• Document architecture specifications; work with ASIC design, software, and VLSI teams to review and explore trade-offs, define solutions, and track progress.

• Collaborate with other functional teams (Design, Floorplan, Packaging and Systems Engineering, etc) to validate packaging choices against performance, cost, and scalability targets.

What we need to see:

• Master’s/PhD in Computer Engineering, Computer Science or related fields (or equivalent experience)

• A minimum of 8 years of relevant work experience in GPU or CPU System Architecture development

• Proficiency in data analysis (Python, Excel) to correlate configuration changes with performance metrics.

• Deep understanding of accelerated computing and AI data center requirements and tradeoffs, including performance bottlenecks, TCO, Power Delivery Network (PDN), DC Networking, etc

• Strong communication and interpersonal skills, as well as the ability to thrive in a dynamic, collaborative, distributed team.

Ways to stand out from the crowd:

• Experience with GPU architecture, especially in off-chip IO, memory subsystem, and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT, and power management

• Expertise in analyzing performance scaling and bottlenecks at device and system levels for AI/accelerated computing workloads

• Knowledgeable in modern packaging technologies, and their costs and benefits

• Consistent track record of efficiently implementing complex architectural features

• Outstanding problem-solving skills with a focus on optimizing performance, area, complexity, and power