Senior Mask Layout Design Engineer jobs at Nvidia in Taiwan, Hsinchu
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Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. You'll work with ASIC and...
Front-end design, quality checks for our display subsystem/IP. Co-work with verification engineers to ensure that the design is functional. Analyze design trade-offs and optimize design based on features, requirements, and...
Work with analog designers to create accurate systemVerilog model of analog components such as closed-loop PLL, Rx CTLE, SAR ADC and also optics components. You’ll work with system architects, digital...
Define circuit requirements and complete design from schematic, layout, and verification to characterization. Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. Take responsibility for the architecture,...
STA for hierarchical design. Constraints creation and validation, timing budget. Timing closure for both partition and full chip level. Special timing closure, such as io, test, clock etc. Synthesis, Netlist...
You will be working with ASIC controller teams to define a unified interface. Help in streamlining workflows with proper scripts to increase efficiency and enables reusability. Be actively involve in...
Work on architecture and design of our state-of-the-art high speed coherent interconnects (NVLINK-C2C) for our mobile SoCs and GPUs. Collaborate with architects, external partners, software engineers, and circuit designers to...
Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools. You'll work with ASIC and...
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