Senior Swqa Test Development Engineer jobs at Nvidia in Romania, Iași

What you’ll be doing:

• Create automation tests based on manual scenarios and be involved in enhancing framework architecture and implementation for areas such as UI, REST API, process automation, and performance validation;

• Assist in building reliable fast feedback loops by integrating automation testing in CI and discovery pipelines;

• Help build testing-related documentation, including test plans, test cases, and bug reports;

• Manage bug lifecycle and collaborate with multi-functional teams to work towards solutions.

What we need to see:

• Currently pursuing a BS or higher degree in CS/EE/CE or related field

• Programming skills in Python or similar languages;

• Understanding of Unix/Linux and shell scripting basics;

• Hands-on experience using AI development tools;

• Strong attention to detail, problem-solving skills, and quality-focused attitude;

• Good communication skills in written and verbal English;

• Passion to learn new technologies and grow your skills.

Ways to stand out from the crowd:

• Academic or personal projects involving AI/ML, especially with LLMs or prompt engineering;

• Experience with test automation frameworks or building testing tools;

• Familiarity with NVIDIA GPU hardware;

• Coursework or projects in distributed systems, performance testing, or data analysis;

• Experience with version control systems (Git) and collaborative development workflows.

November 29, 2025.

Please note: We will be reviewing applications on a rolling basis as they are submitted. We encourage you to apply early.

• Review product requirements and develop test matrix;

• Build testing-related documentation, including test plans, test approach, test cases, and bug reports assessing quality and associated risks;

• Manage bug lifecycle and co-work with inter-groups to work towards solutions;

• Automate manual tests and assist in the architecture, crafting and implementing test frameworks.

• Enhance the existing testing frameworks used in the organization by our engineers, including yourself, for areas such as UIs, REST APIs, process automation, and performance validation;

• Build a reliable fast feedback loop by integrating automation testing in CI and discovery pipelines.

• BS or higher degree or equivalent experience in CS/EE/CE plus equivalent with 5+ years QA experience;

• Proficient with web-based UI and RESTful APIs validation via code as well as Unix/Linux and Shell/Python programming skills;

• Rich experience in test cases development and failure root cause analysis;

• Good command of Cloud management systems and Kubernetes / Docker / Podman;

• Experience with building and handling CI/CD pipelines;

• Hands-on experience working with Large Language Models (LLMs), including prompt engineering, fine-tuning, or integration into QA workflows;

• Fine-tuning or training models for QA-specific tasks – adapting LLMs or other models specifically for testing, documentation analysis, or requirement validation;

• Good QA sense, including attention to detail, problem-solving, data analysis, quality standards knowledge, time management etc.;

• Excellent communicator, fluent written and verbal English;

• Good teamwork skills with the ability to work independently; passion to learn new technologies.

• Experience building AI systems such as RAG (Retrieval-Augmented Generation) pipelines, MRC (Machine Reading Comprehension) solutions, or AI agents;

• Building AI-powered test generation tools – using LLMs to automatically generate test cases, edge cases, or synthetic test data;

• Experience working with NVIDIA GPU hardware is a strong plus;

• Scalability or performance testing knowledge is a plus;

• Experience with data analysis and system monitoring across distributed systems.

What you will be doing:

• STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

• Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.

• Taking part inflows development.

What we need to see:

• B.SC. in Electrical Engineering/Computer Engineering.

• 3-6 years of experience as STA engineer.

• Ability to quickly adapt to new technology and go deep into new areas

• Strong communication skills

• Great teammate.

• Drive new solutions based on any issues that arise

Ways to stand out from the crowd:

• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

What you will be doing:

• Full Chip Layout implementation and analysis of partition groups / top-level according to specifications, under challenging constraints, targeting for the area, route and integration.

• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex layout and congestion problems.

• Daily work involves all aspects of layout implementation and analysis - DRC, LVS, ANT for partition groups and full chip level.

• Taking part inflows development.

What we need to see:

• B.SC. in Electrical Engineering/Computer Engineering.

• 4-6 years of experience as BE/LO engineer.

• Ability to quickly adapt to new technology and go deep into new areas

• Strong communication skills

• Great teammate.

• Drive new solutions based on any issues that arise

Ways to stand out from the crowd:

• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

What you will be doing:

• Backend Integration steps of blocks/top-level connectivity according to specifications under challenging constraints targeting for the best area, route and performance.

• Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Planning next generation chips integration implementation. Resolving complex integration and implementation problems.

• Daily work involves all aspects of integration - frontend / backend dependencies, reuse, connectivity planning and analysis.

• Taking part inflows development.

What we need to see:

• B.SC. in Electrical Engineering/Computer Engineering.

• 4-6 years of experience as BE / Integration engineer.

• Ability to quickly adapt to new technology and go deep into new areas

• Strong communication skills

• Great teammate.

• Drive new solutions based on any issues that arise

Ways to stand out from the crowd:

• Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).