Principal Design Engineer Analog Ic jobs at Marvell in United States, Irvine

As an intern, you’ll work alongside world-class engineers on real silicon for next-gen data communication. You’ll gain hands-on experience in the design, layout, and verification of high-speed analog and mixed-signal circuits using advanced BiCMOS and FET technologies.As a member of the design group, the candidate will be responsible for design, layout and verification of FET and BiCMOS circuits for high-speed broadband ICs that serve these applications.

What You Can Expect

• Understand the requirements of the product and how your block fits into it.
• Capture schematics in Cadence Virtuoso
• Investigate new architectures to come up with the best choice for the requirements.
• Perform layout of an integrated circuit block.
• Create an extracted model of the design.
• Run simulations to verify the performance of the design.
• Document the design and hold a design review with the design team.

What We're Looking For

Looking to fill a 4 to 8 month position with a flexible start date.

• Candidate MUST be currently pursuing a MSc or PhD degree in EE or related technical field(s)
• Detailed understanding of various different circuit blocks such as:
• Opamps, VGAs, High Speed Drivers, TIAs, Mixers, VCOs.
• Ability to analyze feedback networks.
• Familiarity with layout.
• Understanding of device physics.
• Strong communication, presentation, and documentation skills

• Knowledge of Cadence design software.
• Knowledge of SiGe Bipolar as well as CMOS is a plus.
• Ability to perform electro-magnetic analysis and simulation of planar inductors, trasmission lines and t-coils.
• 0-4 years of previous industry experience

Custom Compute and Storage Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements in CCS BU.

What You Can Expect

• The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs
• The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space.
• In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs.
• The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience.
• Hands on working experience in various stages of DFT-Execution -SCAN/MBIST/Validation/STA/IP-DFX/Post-SiliconBringup/Debug
• Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs.
• Strong fundamentals in Digital Circuit Design and Logic Design is required
• Understanding of DFT Flows and Methodologies and Experience withCadence/Mentor/SynopsysTool set (Genus,Modus,NCSim /DC,Tessent,Spyglass/Tmax)
• Prior experience in ASIC design is a plus
• Scripting skills using PERL, Tcl and C-Shell is plus

As a Senior Staff Engineer, Digital IC Design with Marvell, you’ll be a member of the Automotive business group. In Automotive BG, you will be involved in developing next-generation high-speed communication low-power Automotive Ethernet Switch and focus on micro-architecture, RTL coding, verification, and synthesis. Furthermore, you will participate in all silicon development aspects and work closely with engineers from different departments to bring the project from concept to production.

What You Can Expect

• Build knowledge of overall architecture of Automotive and Networking Ethernet products.

• Follow industry standards and initiate documents for enhancing or implementing features on our products.

• Deliver various functional and design specifications for design, verification, and system teams.

• Work together with verification engineers for design verification and validation.

• Collaborate with the physical design engineers to achieve timing, area, and power goals.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or a Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

• Independently analyze and optimize small sub-circuit blocks within our overall design across Process, Voltage, and Temperature.

• Responsible for at least one major sub-circuit block from architecture definition to fine tuning.

• Experience identifying and proposing innovative solutions to enhance the design of at least one major sub-circuit block.

• Experience in root cause investigation and silicon validation of model to hardware correlation issues.

• Have hands-on experience for all aspects of the chip development process with proficiency in front end tools and methodologies.

• Knowledge of Ethernet protocol or previous experience with network IC development is a plus.

Expected Base Pay Range (USD)

124,160 - 186,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing highly sophisticated CMOS transceiver/SERDES products.Responsibilitieswould include implementation and verification of circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as Spectre, MATLAB etc.

What We're Looking For

·Hands-on experience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits.
·Specialized depth and/or breadth of expertise.
·Ability to apply innovative solutions to resolve complex issues.
·History of identifying and developing best practices that deliver high-quality and effective solutions.
·Strong knowledge on the deep sub-micron CMOS technologies.
·Knowledge and experience on low power and high speed design techniques.
·Excellent problem solving and analytical skills.
·Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc.
·Lab testing skills to evaluate the prototype unit to the design specification.
· Completed a MS in Electrical Engineering with 15+ years of related experience or PhD degree in Electrical Engineering with 12+ years of related experience.

Expected Base Pay Range (USD)

170,100 - 251,750, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at