Analog Design Engineer Senior Principal jobs at Marvell in Italy

What You Can Expect

The hardware application engineering position focuses on resolving customer issues on their HW/platform, customer design enablement, bring-up, and manufacture production. The candidate should have strong working knowledge of the major computer industry standards such as PCIe Express, Ethernet, and miscellaneous interface.

• Debug L1 ethernet issues related to Serdes and MAC/PHY (analyze Signal Strength, Serdes Eye, Review & Tune SI parameters etc.).

• Debug other interfaces on board such as PCIE, i2C, MDIO etc.

• Perform Schematics and Layout reviews of the customer design / platform and provide feedback.

• Interact with HW designers (board and ASIC) and write Hardware Design guidelines, Application Notes and publish Technical Bulletins.

• Interface with board designers, ASIC /Serdes controller designers, program management, board vendors and component vendors to fully comprehend the board design parameters.

• Generate PCB stack up recommendations that comprehend the full capabilities of industry available board fabrication materials and technologies.

• Communicate effectively with customers considering both strategic and tactical aspects of the solution & work with internal cross-functional teams to deliver optimal solutions.

Basic Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.

• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

• Must possess excellent written and verbal communication skills.  Be able to present and clearly articulate solutions to customers.

• Previous experience of working as an Application Engineer or any equivalent Customer interacting role (i.e. ability to handle customers) is a must.

• Expertise in High Speed Ethernet Serdes interfaces : NRZ, PAM-4 100G.

• Expertise in Ethernet Physical layer (Layer 1) - Serdes, MAC, PCS including debugging L1 issues for Interop.

• Strong background in Signal Integrity, Power Integrity, Electromagnetics, Thermal, Multi-lane cross talk analysis and RF applications related to IC Package and PCB Design are required.

• Experience in using tools: HyperLynx, Ansoft SIWave and HFSS, ADS, Sigrity, PowerSI and PowerDC, Cadence Allegro, and Polar stack up.

• Able to perform Schematics & Layout reviews effectively.

• At least one of the following scripting languages: Python / Perl / Unix shell.

Preferred Qualifcations

• Expertise in MATLAB and Python a plus.

• Ability to handle Equipment: Servers (Windows / Linux), Scopes, Traffic generators (Ixia/Spirent/Xena), environmental chambers, Thermal Heads, Keysight VNA/TDR.

• Ability to program High speed / optics modules and link up with various modules: LR, SR, ZR, ZR4, AECs etc.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

Key responsibilities of a Technical Program Manager:

• Customer Relationship Building:

Develop strong relationship with customer and be a strong advocate for customer within the organization.

• Project Planning and Execution:

Develop comprehensive project plans, including timelines, milestones, resource allocation, and risk management strategies to meet customer’s product life cycle requirements.

• Cross-functional Collaboration:

Facilitate communication and collaboration between cross functional teams and key stakeholders to ensure alignment on project goals and dependencies.

• Technical Expertise:

Understand test development, DFT, product quality & reliability, and supply sourcing & planning concepts to ensure timely high volume prototype delivery and cost-effective final production ramp.

• Metrics and Reporting:

Track project progress, key performance indicators (KPIs), and identify areas for improvement through regular reporting to leadership.

• Risk Management:

Proactively identify potential risks, develop mitigation plans, and escalate issues to relevant stakeholders and leadership.

• Stakeholder Management:

What We're Looking For

• Strong technical background in New Product Development including DFx, test content & program development, data & H/W infrastructure setups, and manufacturing ramp readiness.
• Prior direct experience with Hyperscale customers is required
• Experience in successful release and ramp of Hyperscaler products for high volume production
• Proven project management skills with experience managing complex cross-functional co-development projects
• Excellent communication and interpersonal skills to build relationships and facilitate collaboration
• Analytical and problem-solving abilities to identify and address project challenges and risks
• Leadership skills to guide teams and influencedecision-making
• Proficiency with project management tools and methodologies

Experience & Education

• Minimum 10+ years experience in new product development or co-development with customer
• Bachelor degree in electrical engineering, masters preferred.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

Marvell is seeking an RF and Analog Design Engineer to contribute to the development of multi-tens of GHz transimpedance amplifiers (TIAs). These optical interface chips are tightly coupled with our high-performance equalizers. The results of our innovative designs have made our TIAs best in class for coherent long-haul and metro systems as well as PAM4 data center systems. In this role you will be responsible for:

• Active-circuit design.
• Design of leading edge transimpedance amplifiers, using both SiGe BiCMOS and the most advanced CMOS FinFET technologies, where circuit performance will need to transcend beyond industry leading products.
• Development of transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable.
• Design of high-performance broadband analog circuits for optical front-end receivers.
• Design of various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc.
• Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support.

What We're Looking For

• Bachelor’s degree in Electrical Engineering with 3-5 years of industry experience OR Master’s or PhD degree in Electrical Engineering with 1+ years of industry experience in the area of designing high-performance RF/Analog Receiver/TIA.
• Proven experience in high-performance receiver design including both chip tape-out AND lab evaluation.
• Solid experience in.
  • Using EDA CAD tools
  • Performing Analog Custom Layout
• Experience in measuring IC performance and debug of design to correlate simulations to measurements.
• Deep understanding of fundamentals, including:
  • Detailed transistor level design.
  • Device physics.
  • Control/Feedback loop stability analysis.
• Direct project experience in at least one of the following areas is a plus:
  • Automatic gain-control loops.
  • High precision analog circuits including linear regulators, current sensors, bandgaps and DAC/ADC.
  • Continuous-time linear equalizers.
• Experience in Package-System integration issues is desired.
• Project experience in using different technologies. (SiGe BiCMOS and FinFET CMOS are pluses)
• A team-player.
• Experience in the following is a plus:
  • Overseeing and mentoring junior circuit designers.
  • Experience as chip lead with success in silicon.
  • Experience in taking chips to mass production.
  • Ability to translate chip level specifications into architecture.
• Strong communication, presentation and documentation skills.