Jobs at Marvell in Canada, Vancouver

What You Can Expect

As a Principal FAE, you will:

• Serve as the key technical interface during the pre-sales phase , supporting the sales team with product knowledge, solution positioning, and hands-on demonstrations.
• Provide timely, expert-level responses to customer issues , working across hardware and software layers.
• Assist customers with software bring-up, protocol integration, and system debug using Marvell's switch silicon and SDK.
• Guide customers through implementation of networking protocols (e.g., VLAN, STP, L2/L3 routing) and best practices.
• Deliver training sessions and workshops to enable customer engineering teams.
• Create and maintain technical documentation, user guides, and application notes to support customer development.
• Review customer schematics, layouts, and design documentation for switch-based systems.
• Troubleshoot and resolve issues through email, phone, remote sessions, or on-site support when needed.
• Collaborate with internal Marketing, Engineering, and Architecture teams to define and influence next-generation switch products and tools .
• Support regular travel to customer sites, engineering centers, and internal meetings (approximately 20–30%).

What We're Looking For

• 8+ yearsof experience in embedded software or system design
• Strong programming skills in C and C++
• Deep understanding of networking fundamentals – VLAN, STP, L2/L3 routing, TCP/IP stack
• Proficient in Linux (User Space, Kernel, and Device Drivers)
• Familiar with Embedded Operating Systems and RTOS architecture
• Excellent verbal and written communication and presentation skills
• Self-motivated, customer-focused, with strong troubleshooting skills

Preferred Qualifications:

• Strong knowledge of PCIe interface protocols
• Hands-on experience with high-speed serial interfaces like SGMII, XFI, XAUI/RXAUI, SFI, 100M/1G/10G Ethernet
• Familiarity with Marvell switch silicon and SDKs is a significant plus
• Experience with PCB layout reviews, signal integrity , and board bring-up
• Skilled in using lab equipment such as oscilloscopes, logic analyzers, traffic generators , and protocol analyzers
• Prior FAE experience or customer-facing engineering role highly desirable

Education:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science , or related field

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

• Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes(Serializer/Deserializer)die-to-die communication and high-speed wireline design.
• Design of analog mixed-signal blocks such as: ADCs, DACs, Regulators, Clock Generation and Distribution, DLLs, Custom high-speed digital circuits, CTLE, VGA, and TX Drivers.
• Supervise and guide layout activities to ensure design accuracy and performance.
• Conduct post-silicon testing and validation of analog mixed-signal circuits.
• Collaborate with cross-functional teams to ensure successful project execution.
• Utilize state-of-the-art EDA tools for design automation and verification.
• Prepare and maintain detailed documentation of design processes and results.
• Prepare and participate in design reviews to ensure design quality and compliance with project requirements.

What We're Looking For

• MS/PhD in Electrical Engineering and 7+ years of demonstrated experience in analog mixed-signal design, specifically in one or more of the following areas: ADC, DAC, voltage regulators, clock generation and distribution circuits, DLLs, custom high-speed digital circuits, CTLE, VGA, and TX drivers.
• Expertise in high-speed and low-power design within advanced CMOS technologies, including knowledge of trade-offs and optimization techniques for performance and power efficiency.
• Ability to identify, analyze, and resolve complex design issues, ensuring robust and reliable circuit performance.
• Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements.
• Experience in post-silicon validation, including hands-on experience with lab equipment, debugging, and characterization of analog mixed-signal circuits.
• Good understanding of CMOS process technology, device physics, and the impact of process variations on circuit performance.
• Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics
• Strong communication, presentation and documentation skills.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

Responsibilities would span working with team on architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.

What We're Looking For

Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 5+ years of experience.A successful candidate should have experience in some of the following designs:

• PLL, Data Converters, Oscillators and high-speed SerDes design including Receiver and Transmitter design.
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.
• Good understanding of analog layouts in FinFet and its effect on high-speed designs
• Experienced in system level pre-tape out analog validation
• Experienced in lab chip bring-up and debugging efforts
• Strong leader and communicator.

What You Can Expect

Design IP that includes but not limited to 112G/56G PAM4; 32G PAM2; DDR; Die-to-Die High Speed Interconnect; System PLL IPs.

Provide the instructions to the layout engineers.

Working with the AE for the IP characterization and validation plan.

Supporting IP Lab characterization and debugging.

What We're Looking For

Master’s degree with 5+ years of related professional experience and/or PhD in Electrical Engineering with 3+ years of experience.

• Experience in high speed analog mixed signal design in 7nm and below for TSMC process.
• PAM4, 56G or 112G SerDes Design experience highly desired
• Demonstrable knowledge of high performance SerDes development
• Demonstrable team player and works well in a collaborative environment
• Project leading and SOC support is preferred
• Strives to make others better

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

What We're Looking For

a highly skilled and motivatedSaaS andCloud Access Security Platformto join our Information Security team. This role will be pivotal in ensuring secure access toapplications and safeguarding organizational data in the context of AI technologies. The ideal candidate will have deepin CASB solutions,SaaS access security,data loss prevention, and developing robust security strategies to enable safe technology adoption.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at.