Senior Layout Designer jobs at Intel

Job Description:

) is at the forefront of silicon photonics integration and is part ofData Center, connected computing-devicesnearly aand higher speeds from 400G today to 1.6T+ and beyond tomorrow. We are looking forgreat talentto accelerate thisso if you are interested in joining our leadingthen we want to hear from you.

The team is seeking an experienced Hardware Designer with expertise in SI and PI to support the development of reference module designs, PIC sub-system EVB and other test boards to support product development. Demonstrated expertise in designing 100G/lane and 200G/lane module PCBA, lead the layout execution for high-speed traces, power delivery, require extensive experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage tradeoffs in design. The candidate will be expected collaborate with a cross functional product development team - HW, FW, PIC, EIC, Packaging and thermal, Optics and NPI.

Job responsibilities include but are not limited to:

• Perform SI simulations of high-speed interfaces, RF traces, etc. 100Gbps, 200Gbps NRZ and PAM4 signaling.
• Modeling of high speed traces with vias, connectors, sockets and various system components in 3D EM tools like HFSS, ADS.
• Design and optimize Power Delivery Network (PDN) across packages and PCBs.
• Perform PI sims for IR drop, current density violations, dynamic switching noise analysis to validate board designs.
• Expertise in designing 100G/lane and 200G/lane module PCBA, lead the layout execution for high-speed traces, power delivery, require extensive experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage tradeoffs in design.
• Ability to lead hardware design of an optical transceiver and evaluation boards including schematic design, circuit simulation, PCB layout floor planning, design with layout engineer is a plus.
• Lead PCB bring up working with FW engineers to confirm functionality w.r.t design targets. Validate PCB high speed designs thru product design verification tests and independent PCBA characterization. Troubleshoot and optimize performance of thesub-system/transceivermodule boards.
• Extensive experience with selection of DSP, Driver, TIA, uControllers, DACs, ADCs, Voltage regulators, etc.
• Key contributor to Product Requirements, Owns PCBA design from concept phase to full final design and EVT/DVT phase of the product.
• Understand electrical and optical requirements and specifications of optical transceiver MSA. Like 800G DR8/2xFR4, 1.6T DR8/2xFR4, 800G LPO, 1.6T LRO etc.
• Maintain documentation of a hardware design specification, Pass design check list prior to tape out, BOM specifications and work with NPI team to build PCBA. Lead design reviews and present design summary to management, highlight risks with mitigation plans.
• Interface and work collaboratively with mechanical engineers, optical engineers, Photonics engineer, firmware engineers, process engineers and test engineers.
• Interact with program manager, buyer/planner and suppliers to make sure designed parts are available in a timely manner for build and test.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• M.S. in Electrical Engineering
• 4+ years of HW/circuit design experience
• 4+ years of experience in:
  • transceiver electrical design principles, including high speed signal integrity, crosstalk, power integrity, noise, ESD, FW, testing, etc.
  • layout and able to direct layout engineer with clear design priority
  • PI and SI tools (HFSS, ADS, Cadence)
  • high density multiple-layer board design.
  • high volume PCB/substrate fab houses.

Preferred Qualifications

• Ph.D. in Electrical Engineering
• Strong analog and digital circuit design skills and layout with mixed signal designs.
• Experience working with AWG, DCAM, VNA/LCA to characterize high speed performance
• Strong laboratory optical and electrical measurement skills.
• Strong communication and presentation skills.
• Experience with micro-controllers and communication protocols such as SPI, I2C, MDIO, CMIS management interface for optical modules.
• Strong background of digital communication theory.
• Familiarity with industry standards including IEEE Ethernet standards, OIF standards, PCIe standards and various MSAs.
• Experience with optical transceiver test and calibration methodologies.
• Experience working with Marvell, Broadcom, MaxLinear, Credo DSPs in pluggable optical modules.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 161,230.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

We are seeking a Senior Device Engineer to drive the development of next-generation CMOS device technologies in our high-volume manufacturing environment. You will collaborate with cross-functional teams to develop innovative semiconductor solutions, optimize manufacturing processes, and deliver customized device architectures that meet our foundry customers' most demanding requirements.

Key Responsibilities

Data Analysis and Optimization: Utilize advanced data analysis, scripting, and analytical techniques to accelerate learning and drive continuous improvement. Interpret complex product data including inline, e-test, and SORT data to identify failure root causes and develop effective solutions.

Adaptability andProblem-Solving -Navigating changing technology landscapes while troubleshooting complex issues under tight timelines.

Qualifications:

Bachelor's Degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering, device physics, logic architecture, and interconnect development on leading-edge technology nodes.

The experience must include:

• Advanced CMOS device technology, preferably in a foundry environment.
• Foundry NPI. Device targeting and corner skew.
• IC wafer fabrication process engineering, manufacturing systems, semiconductor materials, and wafer testing across various fabrication areas including photolithography, advanced patterning, thin film deposition, planarization, defect metrology, and spectroscopy.
• Interpreting product data including inline, e-test, and SORT data, finding failure root cause and inline indicators, and driving for solutions.

Preferred Qualifications

• Post-graduate degree in Electrical Engineering, Physics, or related field with 6+ years of specialized CMOS device engineering experience.
• Direct hands-on experience in advanced node semiconductor technology development, particularly with 3nm-16nm FinFETs and sub-3nm GAA FETs.
• Experience in high-volume manufacturing environments with proven ability to balance foundry and customer needs.
• Expertise in Process Design Kit (PDK) silicon model target generation,silicon-to-simulationcorrelation, test structure design, device modeling, and electrical characterization.
• Direct customer-facing experience with familiarity in industry standards and certifications.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 117,140.00 USD - 226,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

• Develop and validate detailed finite element analysis (FEA) models to simulate thermal and mechanical behavior of advanced semiconductor packages. Perform simulations to evaluate stress, strain, warpage, thermal cycling, and reliability risks across a wide range of package architectures.

• Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations. Design and coordinate lab tests and research on materials and properties to understand material behavior and reliability failure mechanisms.

• Support technology roadmap development by evaluating new materials, interconnect structures, and process flows from a thermo-mechanical reliability perspective.

• Drive design-of-experiment studies and sensitivity analyses to understand key drivers of package performance and reliability

• Contribute to the development and automation of internal simulation workflows, tools, and best practices to improve modeling efficiency and accuracy

• Develop solutions to problems utilizing formal education, experience and engineering judgment

• Communicate recommendation and solution space to internal and external customers. Responds to customer/client requests or events as they occur.

• Document and present simulation methodologies, results, and recommendations to both technical and executive audiences

• Stay current with industry trends, emerging technologies, and academic research in advanced packaging and simulation methodologies

• Strong communication skills across internal and external stakeholders andplanning/prioritizationskills for project success

• Ability to handle ambiguity and use appropriate skills (behavioral and/or technical) to drive clarity across stakeholders

• Willingness to lead and influence both external and internal teams

• Willingness to work independently with minimal supervision

• Technical problem-solving skills in a highly dynamic team environment

This role requires regular onsite presence to fulfill essential job responsibilities. Provides tactical and strategic operational support to ensure the successful development and ramp of a high volume or technology development fabrication facility.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.Minimum Qualifications:

• Master's Degree in Mechanical Engineering, Chemical Engineering, Material Sciences or a related field and 7+ years of industry experience

• -OR- PhD Degree in Mechanical Engineering, Chemical Engineering, Material Sciences or a related field and 4+ years of industry experience

Industry experience should include the following:

• Thermo-mechanical FEA modeling in semiconductor packaging domain

• At least one of the commercial FEA tools such as ANSYS, ABAQUS and COMSOL

• Advanced packaging technologies such as Foveros, EmIB, Cowos and Hybrid bonding.

• Semiconductor packaging processes, including die attach, underfill, molding, bumping, surface mount and reflow.

Preferred Qualifications:

• Experience with multi-physics simulations, including coupledelectro-thermal-mechanicalanalysis, free surface two phase flows, electroplating and plasma

• Familiarity with JEDEC reliability standards and qualification tests

• Experience with scripting and automation (e.g., Python, TCL, MATLAB) to streamline simulation workflows

• Experience in technical program management in any assembly or test functional area

• Experience in driving yield improvement activities for advanced package architectures

• Previous related work experience in asemiconductor foundry preferred

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 264,470.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:Qualifications:Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix, US, Texas, Austin
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 132,810.00 USD - 258,410.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Physical Design Implementation

• Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases
• Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex

CPU Cores

• Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs
• Optimize CPU designs to improve critical product parameters including power, frequency, and area

Verification & Signoff

• Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis
• Perform reliability verification, static and dynamic power integrity analysis, and layout verification
• Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance
• Ensure design quality and manufacturability across all verification domains

CPU-Specific Expertise & Optimization

• Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure
• Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization
• Implement design-for-test (DFT) methodologies specific to CPU architectures
• Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures

Technology Leadership & Innovation

• Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design
• Analyze design results and provide recommendations to improve current and future CPU microarchitectures
• Participate in development and improvement of physical design methodologies and flow automation
• Drive adoption of advanced design techniques and emerging technologies

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• 5+ years of experience in VLSI circuit design and synthesis
• 4+ years of experience in static timing analysis
• 4+ years of experience in low power design methodologies
• Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics)
• Experience with timing closure, power optimization, and signal integrity analysis

Preferred Qualifications

• Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• Experience with x86 CPU architecture and Intel processor designs
• Experience with Tcl, Perl, Python Programming
• Experience in CPU microarchitecture and high-performance design principles

What We Offer

• Competitive compensation and comprehensive benefits
• Opportunity to work on industry-leading CPU architectures and technologies
• Access to cutting-edge EDA tools and advanced process technologies
• Collaboration with world-class CPU architects and design engineers
• Professional development and career advancement opportunities
• Direct impact on products powering global computing infrastructure

Experienced HireShift 1 (United States of America)US, California, Folsom
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Role Overview:

The Senior Thermal Architect will lead thermal design and strategy for next-generation GPU, AI accelerators, and data center products. This role is critical to enabling high-performance computing at scale while meeting stringent thermal requirements. You will define thermal architecture across silicon, package, and platform levels, ensuring optimal thermal performance for products approaching multi-kilowatt levels:

Key Responsibilities:

• Define and deliver advanced packaging thermal solutions for advanced GPU/AI products
• Architect thermal strategies for 3DIC and advanced packaging technologies, including chiplets and heterogeneous integration.

• Develop analytical and experimental methods for thermal characterization and prediction.
• Drive co-optimization of thermal, electrical, and mechanical design across silicon, package, and system levels.

• Push the boundaries of thermal management to support Moore's Law progression.
• Evaluate and integrate emerging cooling technologies (e.g., liquid cooling, immersion cooling) for data center sustainability.

• Partner with silicon design, packaging, and platform teams to ensure thermal compliance and performance.
• Engage with external customers and ecosystem partners to align thermal solutions with product requirements.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences

Minimum Qualifications

• MS or PhD in Mechanical Engineering, Thermal Sciences, or related field.
• 10+ years in thermal design of semiconductor products
• Proven track record in thermal architecture and advanced packaging.
• Proficient in thermal simulation tools (e.g., CFD, FEA) and experimental validation.

Preferred Qualifications

• 10 + years experience in high-performance computing or data center products.
• Proven track record in GPU/AI thermal architecture and advanced packaging.
• Experience with rack-scale cooling solutions and liquid cooling technologies.
• Familiarity with AI/GPU performance trends and their thermal implications.
• Strong understanding of power delivery, energy efficiency, and cooling technologies.
• Ability to influence architecture decisions and drive innovation across global teams.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 136,990.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

You will have the opportunity to work with partners in Technology Development (TD), Design Technology Platform (DTP), and a world class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.

Primary responsibilities include but are not limited to:

• Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bitcells, SRAMs, Register Files).
• Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
• Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom auto-routers and custom placers to efficiently construct layout.
• Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.
• Develops and drives new and innovative layout methods to improve productivity and quality.
• Troubleshoots a wide variety of issues up to and including design andtool/flow/methodologyissues used for layout design.

Additional responsibilities:

• Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies.
• Defines methodologies for hardware development related to technology node and EDA tool enabling.
• Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes.
• Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.
• Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.
• Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power, and performance clocking, and/or timing to enhance future TFM development.
• Collaborates with EDA vendors on defining and early testing of next-generation design tools.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

• Bachelor's degree in Electrical/Computer Engineering or related field and 6+ years of experience OR a Master's degree in Electrical/Computer Engineering or related field and 4+ years of experience OR a PhD in Electrical/Computer Engineering or related field and 2+ years of experience in:
  • Layout design & Cadence Virtuoso

Preferred qualifications:

• 6+ years of experience in:
  • CMOS VLSI design concepts, flows, and EDA tools
  • Programming/scriptingin C/C++, Python.
  • UNIX/Linux operating systems.
• 8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).
• 4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development
• 1+ year of experience with Cadence SKILL programming languages.
• Experience leading and coordinating small/medium size group of layout designers.
• Strong initiative, analytical/problem solving skills, communication skills, team working skills, ability to multitask and be able to work with a diverse team located in different geos.

Experienced HireShift 1 (United States of America)US, Oregon, HillsboroUS, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 227,620.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.