Gpu Validation Engineer jobs at Intel

Physical Design Implementation

• Execute complete physical design flow for custom CPU designs from RTL to GDS, creating manufacturing-ready design databases
• Perform synthesis, place and route, clock tree synthesis, floorplanning, and power/clock distribution for complex CPU cores
• Conduct static timing analysis, reliability analysis, and power/noise analysis for high-performance processor designs
• Optimize CPU designs to improve critical product parameters including power, frequency, and area

Verification & Signoff

• Execute comprehensive verification and signoff processes including formal equivalence verification and static timing analysis
• Perform reliability verification, static and dynamic power integrity analysis, and layout verification
• Conduct electrical rule checking (ERC) and structural design checking to ensure manufacturing compliance
• Ensure design quality and manufacturability across all verification domains

CPU-Specific Expertise & Optimization

• Apply specialized knowledge in CPU structural and physical design including physical clock design and timing closure
• Perform coverage analysis, multiple power domain analysis, structured placement, and routing optimization
• Implement design-for-test (DFT) methodologies specific to CPU architectures
• Collaborate closely with logic, circuit, architecture, and design automation teams to optimize microarchitectures

Technology Leadership & Innovation

• Work with industry EDA vendors to build and enhance tool capabilities for high-speed, low-power synthesizable CPU design
• Analyze design results and provide recommendations to improve current and future CPU microarchitectures
• Participate in development and improvement of physical design methodologies and flow automation
• Drive adoption of advanced design techniques and emerging technologies

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• 2+ years of experience in VLSI circuit design and synthesis
• 1+ years of experience in static timing analysis
• 1+ years of experience in low power design methodologies
• Experience with physical design EDA tools (i.e. Synopsys, Cadence, Mentor Graphics)
• Experience with timing closure, power optimization, and signal integrity analysis

Preferred Qualifications

• Postgraduate degree (Master's/PhD) in Computer Engineering, Computer Science, Electrical Engineering, or STEM-related field of study
• Experience with x86 CPU architecture and Intel processor designs
• Experience with Tcl, Perl, Python Programming
• Experience in CPU microarchitecture and high-performance design principles

What We Offer

• Competitive compensation and comprehensive benefits
• Opportunity to work on industry-leading CPU architectures and technologies
• Access to cutting-edge EDA tools and advanced process technologies
• Collaboration with world-class CPU architects and design engineers
• Professional development and career advancement opportunities
• Direct impact on products powering global computing infrastructure

Experienced HireShift 1 (United States of America)US, California, Folsom
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 104,890.00 USD - 197,230.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Job Description:

) is at the forefront of silicon photonics integration and is part ofData Center, connected computing-devicesnearly aand higher speeds from 400G today to 1.6T+ and beyond tomorrow. We are looking forgreat talentto accelerate thisso if you are interested in joining our leadingthen we want to hear from you.

The team is seeking an experienced Hardware Designer with expertise in SI and PI to support the development of reference module designs, PIC sub-system EVB and other test boards to support product development. Demonstrated expertise in designing 100G/lane and 200G/lane module PCBA, lead the layout execution for high-speed traces, power delivery, require extensive experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage tradeoffs in design. The candidate will be expected collaborate with a cross functional product development team - HW, FW, PIC, EIC, Packaging and thermal, Optics and NPI.

Job responsibilities include but are not limited to:

• Perform SI simulations of high-speed interfaces, RF traces, etc. 100Gbps, 200Gbps NRZ and PAM4 signaling.
• Modeling of high speed traces with vias, connectors, sockets and various system components in 3D EM tools like HFSS, ADS.
• Design and optimize Power Delivery Network (PDN) across packages and PCBs.
• Perform PI sims for IR drop, current density violations, dynamic switching noise analysis to validate board designs.
• Expertise in designing 100G/lane and 200G/lane module PCBA, lead the layout execution for high-speed traces, power delivery, require extensive experience with designing PDN for high-speed DSP, RFICs, manage PI and SI requirements, actively guide layout engineer and manage tradeoffs in design.
• Ability to lead hardware design of an optical transceiver and evaluation boards including schematic design, circuit simulation, PCB layout floor planning, design with layout engineer is a plus.
• Lead PCB bring up working with FW engineers to confirm functionality w.r.t design targets. Validate PCB high speed designs thru product design verification tests and independent PCBA characterization. Troubleshoot and optimize performance of thesub-system/transceivermodule boards.
• Extensive experience with selection of DSP, Driver, TIA, uControllers, DACs, ADCs, Voltage regulators, etc.
• Key contributor to Product Requirements, Owns PCBA design from concept phase to full final design and EVT/DVT phase of the product.
• Understand electrical and optical requirements and specifications of optical transceiver MSA. Like 800G DR8/2xFR4, 1.6T DR8/2xFR4, 800G LPO, 1.6T LRO etc.
• Maintain documentation of a hardware design specification, Pass design check list prior to tape out, BOM specifications and work with NPI team to build PCBA. Lead design reviews and present design summary to management, highlight risks with mitigation plans.
• Interface and work collaboratively with mechanical engineers, optical engineers, Photonics engineer, firmware engineers, process engineers and test engineers.
• Interact with program manager, buyer/planner and suppliers to make sure designed parts are available in a timely manner for build and test.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• M.S. in Electrical Engineering
• 4+ years of HW/circuit design experience
• 4+ years of experience in:
  • transceiver electrical design principles, including high speed signal integrity, crosstalk, power integrity, noise, ESD, FW, testing, etc.
  • layout and able to direct layout engineer with clear design priority
  • PI and SI tools (HFSS, ADS, Cadence)
  • high density multiple-layer board design.
  • high volume PCB/substrate fab houses.

Preferred Qualifications

• Ph.D. in Electrical Engineering
• Strong analog and digital circuit design skills and layout with mixed signal designs.
• Experience working with AWG, DCAM, VNA/LCA to characterize high speed performance
• Strong laboratory optical and electrical measurement skills.
• Strong communication and presentation skills.
• Experience with micro-controllers and communication protocols such as SPI, I2C, MDIO, CMIS management interface for optical modules.
• Strong background of digital communication theory.
• Familiarity with industry standards including IEEE Ethernet standards, OIF standards, PCIe standards and various MSAs.
• Experience with optical transceiver test and calibration methodologies.
• Experience working with Marvell, Broadcom, MaxLinear, Credo DSPs in pluggable optical modules.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 161,230.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Since pioneering the world’s first hybrid silicon laser, IPS has led the industry in scalable, high-volumemanufacturing andadvanced photonics development. Our mission: deliver next-generation bandwidth growth with smaller form factors, co-packaging, and speeds from 400G today to 1.6T+ tomorrow.

We are seeking a Lead Analog SerDes Architect / Design Engineer to join our team and shape the future of data center connectivity. In this role, you will:

• Defining circuit architecture and enabling designs meeting power, and performance for next generation optical interconnects based on system specifications.
• As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development.
• Specify, architect and design low voltage and low power Mixed-Signal integrated circuits and work collaboratively with digital designers.
• Plan design work with constraints on performance, schedule and quality.
• Provide guidance to junior designers and layout engineers.
• Guidance to develop test plans for post-silicon characterization.
• Document all design work with review materials and detailed design descriptions.

Minimum QualificationsThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.• Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates.
• Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers.
• Experience with design of precision analog circuits like ADC/DACs.
• Experience with designing PAM4/NRZ links.
• Experience with Mixed signal design flow
• Experience with full-chip designs, ESDs and verification flows.
Preferred Qualifications
• Familiarity with Optical communications.
• Experience with 400G/800G/1.6T optical links.
• Experience with package/test setup design.

Experienced HireShift 1 (United States of America)US, California, Santa Clara
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 214,730.00 USD - 303,140.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Intel's Information Security organization enables Intel to provide secure products, solutions, and services which meet U.S. regulatory requirements. The Information Security organization supports the unique IT information Security and Compliance requirements for Intel federal projects that deliver products and/or services to the US Government (USG). As part of this team, you will help us grow our secure solution suite to meet U.S. Government requirements. The Intel Information Security organization is seeking a Senior Infrastructure Automation Developer to join our team. This role is ideal for a technically strong and forward-thinking individual who can lead by example, influence architectural decisions, and drive automation and integration efforts in a highly regulated environment. Business travel is required as needed.Primary Responsibilities:

• Design and implement secure, scalable automation solutions.
• Lead development ofInfrastructure-as-Codeand orchestration tools to improve execution velocity, reduce operational overhead, and enhance system reliability.
• Develop, test, and deploy Ansible playbooks and Python scripts to automate provisioning, configuration, and management of network devices and services
• Collaborate with cross-functional teams to define long-term technical direction and roadmap for secure enclave automation.
• Implement robust monitoring and alerting systems to proactively identify and resolve network issues, leveraging automation for remediation and reporting.
• Package and deploy applications in compliance with IT and federal security standards.
• Troubleshoot and resolve technical issues in automation processes, ensuring high reliability and minimal manual intervention.
• Contribute to system hardening, patching, and compliance automation using industry and DoD standards (e.g., STIG).
• Support system integration, monitoring, and operational continuity.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:

• U.S. Citizenship.
• Ability to obtain a U.S. Government Security Clearance.
• Bachelor's degree and 3+ years of applicable experience.
• 1+ years of experience with CI/CD pipelines and version control systems (e.g., Git, GitHub, GitLab).
• 1+ years of experience in Linux system administration and scripting (Python, Bash, Shell).
• 1+ years of experience withInfrastructure-as-Codetools (e.g., Ansible).

Preferred Qualifications:

• Active U.S. Government Top Secret (TS) Security Clearance with SCI eligibility.
• Bachelor's degree in Computer Science or related field.
• Good understanding of networking fundamentals (TCP/IP, routing, switching, VLANs, firewalls, etc.)
• Ability to thrive in dynamic and fast-paced environments.
• Certifications such as Cisco DevNet, Red Hat Ansible, CompTIA Network+, Python.
• Experience with embedded software development and system integration.
• Experience with Cross Domain Solutions (CDS) and DevSecOps principles.
• Experience with network analysis tools (e.g., Splunk, Wireshark).
• Experience with secure enclave operations.
• Experience network equipment and software-defined networking.
• Strong understanding of IT infrastructure, system patching, and secure deployment practices.

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix, US, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 89,150.00 USD - 173,830.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

WHO YOU ARE

Responsibilities include, but are not limited to:

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

• Maintains and improves existing functional verification infrastructure and methodology.

• Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages and proliferates to future products.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 1+ years of relevant experience

— or —

Master’s degree in the same fields

Relevant work experience should be of the following:

• Experience with UVM
• Experience with System Verilog
• Experience with Design Verification
• Experience with Computer Architecture
• Experience with Hardware Verification

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

College GradShift 1 (United States of America)Virtual US
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 90,890.00 USD - 170,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/25/2026

Job Description:

We are seeking a Senior Device Engineer to drive the development of next-generation CMOS device technologies in our high-volume manufacturing environment. You will collaborate with cross-functional teams to develop innovative semiconductor solutions, optimize manufacturing processes, and deliver customized device architectures that meet our foundry customers' most demanding requirements.

Key Responsibilities

Data Analysis and Optimization: Utilize advanced data analysis, scripting, and analytical techniques to accelerate learning and drive continuous improvement. Interpret complex product data including inline, e-test, and SORT data to identify failure root causes and develop effective solutions.

Adaptability andProblem-Solving -Navigating changing technology landscapes while troubleshooting complex issues under tight timelines.

Qualifications:

Bachelor's Degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering, device physics, logic architecture, and interconnect development on leading-edge technology nodes.

The experience must include:

• Advanced CMOS device technology, preferably in a foundry environment.
• Foundry NPI. Device targeting and corner skew.
• IC wafer fabrication process engineering, manufacturing systems, semiconductor materials, and wafer testing across various fabrication areas including photolithography, advanced patterning, thin film deposition, planarization, defect metrology, and spectroscopy.
• Interpreting product data including inline, e-test, and SORT data, finding failure root cause and inline indicators, and driving for solutions.

Preferred Qualifications

• Post-graduate degree in Electrical Engineering, Physics, or related field with 6+ years of specialized CMOS device engineering experience.
• Direct hands-on experience in advanced node semiconductor technology development, particularly with 3nm-16nm FinFETs and sub-3nm GAA FETs.
• Experience in high-volume manufacturing environments with proven ability to balance foundry and customer needs.
• Expertise in Process Design Kit (PDK) silicon model target generation,silicon-to-simulationcorrelation, test structure design, device modeling, and electrical characterization.
• Direct customer-facing experience with familiarity in industry standards and certifications.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 117,140.00 USD - 226,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Job Description:

• Develop and validate finite element analysis (FEA) models to simulate thermal and mechanical behavior of advanced semiconductor packages. Perform simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across a wide range of package architectures.

• Collaborate with cross-functional teams to define simulation requirements, interpret results, and provide actionable design and process recommendations. Design and coordinate lab tests and research on basic materials and properties to understand material behavior and reliability failure mechanisms.

• The ideal candidate will have to drive strategic development activities and work closely with internal and external customer organizations to plan, execute and communicate development activities and programs.

• The team leverages both experimental and numerical methods across a broad range of areas, including thermal, mechanical, and fluids.

• The team typically uses a combination of simulations and experiments, as needed, to help solve practical engineering problems.

• The team frequently leverages advanced analysis methods (statistical, AI/ML) to supplement modeling and experimental approaches.

Note:This role requires regular onsite presence to fulfill essential job responsibilities. Provides tactical and strategic operational support to ensure the successful development and ramp of a high volume or technology development fabrication facility.

The ideal candidate should exhibit the following skills or behavioral traits:

• Demonstrated ability to work seamlessly between experiments and simulations.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Minimum Qualifications:

• Master's Degree in Mechanical Engineering, Chemical Engineering or Material Sciences or a related field with emphasis in solid mechanics and 3+ years of relevant experience
• -OR- PhD Degree in Mechanical Engineering, Chemical Engineering or Material Sciences or a related fieldwith emphasis in solid mechanics

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US: 100,160.00 USD - 193,390.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.