Cpu Architecture Research Leader jobs at Intel in India, Bengaluru

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
• As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG.
• The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc.
• Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus.

• Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's degree with at least 9 years of experience in DFT.
• Strong knowledge of ATPG, various fault models, fault grading.
• Knowledge of memory BIST, IJTAG/TAP architecture.
• DFT logic generation, integration, and verification.
• EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring uppreferably.
• Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug.
• Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer.
• Post Silicon/ATE Bring-Up Support.
• Experience with RTL (Verilog, System Verilog, VHDL)

• In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII.
• You will be part of ACE Group, in the P-Core design team driving Intel's latest CPU's in the latest process technology.
• Your responsibilities will include but not limited to:Meet the design targets of high performance and low-power digital design, Static timing analysis,Power Optimization, Design Convergence Experience at IP, SoC level.
• Ability to work in a highly dynamic environment across geographies.
• Back end design and implementation of new features.
• Post silicon performance push activities.
• PPA improvement and Methodology improvements

• You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience.
• Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS).
• Preferred Qualifications: - Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting. Strong verbal and written communication skills

* BSc in Computer Science, Industrial Engineering, Information Systems, Data Science, or equivalent.
* Hands-on experience in SQL and complex queries.
* Proven experience in developing BI solutions (dashboards, reports) and ETLs.
* Proficiency in Java, Python, or other object-oriented languages, and REST API calls.
* Experience with BI tools such as QlikSense, PowerBI, or SuperSet.
* Strong communication skills and ability to work independently.
* Fast learner with a positive attitude and strong problem-solving skills.
* Proficient in English.
Advantages:
* Familiarity with Big Data technologies such as Snowflake, Spark, or Athena.
* Experience in HTML, CSS, and JavaScript.
* Knowledge of AI integration with BI tools.
* Understanding of cloud platforms and services related to data analytics.

Your responsibilities will include but not limited to:

1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs.

2. Deep understanding of Static timing analysis concepts

3. Timing Convergence across all HVM targets

4. Closely work with SD, Integration and Floor plan teams

• You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
• In this position, you will be responsible for timing analysis and convergence of complex partitions.
• Your responsibilities will include but not limited to:
• Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs.
• Deep understanding of Static timing analysis concepts
• Timing Convergence across all HVM targets4. Closely work with SD, Integration and Floor plan teams

• You must possess a Masters Degree in Electrical or Electronics Engineering with at least 6 or more years of experience in related field or a Bachelor's Degree with at least 8 years of experience. Technical Expertise in Static Timing Analysis is preferred.
• Preferred additional skills :
• Experience of handle complex core design, high-speed designs
• Timing signoff flows/tools experience both/either Synopsys/Cadence tools
• Very good knowledge on Timing tools, flows and methodology
• Ability to handle new feature feasibility studies
• SD flow knowledge would be plus
• Familiarity with Verilog/VHDL
• Tcl, Perl, Python scripting
• Strong verbal and written communication skills

• In this position, you will be working in a team of enthusiastic engineers on High Speed Designs in P and R from RTL to GDSII.
• You will be part of ACE Group, in the P-Core design team driving Intel's latest CPU's in the latest process technology.
• Your responsibilities will include but not limited to:
• Meet the design targets of high performance and low-power digital design.Static timing analysis.
• Power Optimization: Design Convergence Experience at IP, SoC level.
• Ability to work in a highly dynamic environment across geographies.
• Back end design and implementation of new features.
• Post silicon performance push activities.
• PPA improvement and Methodology improvements

• You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with at least 10 years of experience.
• Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization and P and R tools (CDNS and SNPS)
• Preferred Qualifications: -
• Familiarity with Verilog/ VHDL - Tcl, Perl, Python scripting
• Strong verbal and written communication skills