Sr Phy Design Verification Engineer jobs at Apple in United States, Sunnyvale
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United States
State
Sunnyvale
285 jobs found
14.06.2024
A
Apple Sr PHY Design Verification Engineer United States, California, Sunnyvale
BS and 10+ years of relevant industry experience. Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. Build block/subsystem level test benches...
Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. Build block/subsystem level test benches with reference model, using best in class DV...
BS and 3+ years of relevant industry experience. Verification experience of wireless/wired communication block/subsystem. Excellent knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and...
Ideally at least 7 years of industry experience in wireless PHY design engineering. Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications. Understanding of Decoders - Viterbi, LDPC, Polar....
BS and 3+ years of relevant industry experience. Wireless/Wired communication block/system verification experience. Advanced knowledge of SystemVerilog and DV methodology. Solid verification skills in problem solving, constrained random testing, and...
10+ years SOC verification experience. Expertise in HVL and HDL (SystemVerilog, Verilog). Advanced knowledge of HVL methodology (UVM/OVM/VMM). Solid verification skills in problem solving, constrained random testing, and debugging. Solid...
BS with 10+ years. MSEE/PhD preferred. Experience in Digital Signal Processing, Wireless Communications and wireless chip development. Proven grasp of complex wireless systems with strong capability to comprehend dependencies between...
BS and 10+ years of relevant industry experience. Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. Build block/subsystem level test benches...
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