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Soc Power/performance/thermal Engineering Program Manager jobs at Apple in United States, Beaverton
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Beaverton
32 jobs found
28.07.2025
A
Apple SoC Physical Design Engineer STA/Timing United States, Oregon, Beaverton
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Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and/or Timing Closure. Programming skills with Perl and TCL. Hands-on experience in STA. Familiar with important...
Description:
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
- Minimum BS and 3+ years of relevant industry experience.
- Experience with large design STA and/or Timing Closure.
- Programming skills with Perl and TCL.
- Hands-on experience in STA.
- Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
- Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
- Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
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29.06.2025
A
Apple SoC Power Flow Methodology Engineer United States, Oregon, Beaverton
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A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience. Good understanding of VLSI designs and SOC design flows. Strong passion...
Description:
As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R.Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
- A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience
- Good understanding of VLSI designs and SOC design flows.
- Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions.
- Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java.
- Solid understanding and proven track record using modern software testing and development practices.
- Good written/verbal communications skills are required.
- Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus.
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28.06.2025
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Apple CPU Performance Engineer United States, Oregon, Beaverton
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Minimum BS and 10+ years of relevant industry experience. Experience in CPU performance architecture, performance modeling, micro-architecture design, performance analysis. Experience with C and C++ and at least one of...
Description:
- Minimum BS and 10+ years of relevant industry experience
- Experience in CPU performance architecture, performance modeling, micro-architecture design, performance analysis
- Experience with C and C++ and at least one of the following scripting languages: Perl or Python
- Bachelor of Science or Engineering in Electrical Engineering, Computer Engineering, or Computer Science
- Knowledge and experience with common performance benchmarks and workloads
- Knowledge of OS internals and compiler technology is a plus
- Ability to problem solve and prove your own ideas
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28.06.2025
A
Apple SoC Physical Design Engineer STA/Timing United States, Oregon, Beaverton
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Minimum Bachelor's degree. Experience with STA. Experience with noise, crosstalk, and/or OCV effects. Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies. Experience with STA...
Description:
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.
- Minimum Bachelor's degree.
- Experience with STA.
- Experience with noise, crosstalk, and/or OCV effects.
- Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
- Experience with STA and methodologies for timing closure.
- Familiar with circuit modeling, including SPICE models, and/pr worst-case corner selection.
- Good programming skills with Perl and TCL.
- Experience with large design STA and Timing Closure.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
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07.06.2025
A
Apple CPU Debug Power Management Microarchitect/RTL Engineer United States, Oregon, Beaverton
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Minimum BS and 10+ years of relevant industry experience. Experience with Verilog or VHDL. Experience with simulators and waveform debugging tools. Experience with logic design with timing and power implications....
Description:
As a CPU Debug and Power Management Microarchitect/RTL Engineer, you will own or contribute to the following:• RTL ownership of CPU debug, trace, power management, clock management, and timer logic - development, assessment, and refinement of RTL design to target power, performance, area and timing goals• Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural features, develop micro-architectural details, and arrive at a detailed specification• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - Aid in debug of issues at SoC level related to CPU power management, clock control, and debug features. Work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
- Minimum BS and 10+ years of relevant industry experience
- Experience with Verilog or VHDL
- Experience with simulators and waveform debugging tools
- Experience with logic design with timing and power implications
- Knowledge and understanding of microprocessor architecture
- Expertise in one or more of the following areas: multiple clock/power domains and power management strategies, hardware debug and trace capabilities, DFT strategies, interrupt controllers, memory subsystem queuing, scheduling - starvation and deadlock avoidance, fabric communication protocols and interconnects
- SRAM design basics
- Understanding of low power microarchitecture techniques
- Understanding of high-performance design techniques and trade-offs
- Experience in C or C++ programming
- Experience using an interpretive language such as Python or Perl
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07.06.2025
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Apple SoC Silicon Debug Engineering Program Manager United States, Oregon, Beaverton
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SOC / VLSI Chip Design, Post Silicon Validation or Product Engineering experience. Post-silicon debug experience. Relevant technical program management, technical leadership or vendor management experience. BS and 3+ years relevant...
Description:
In this high profile role you will be responsible for the following:- Drive internal program process to guarantee high quality silicon execution- Focused issue reporting, bug tracking, and communication of program risks & status
- SOC / VLSI Chip Design, Post Silicon Validation or Product Engineering experience
- Post-silicon debug experience
- Relevant technical program management, technical leadership or vendor management experience
- BS and 3+ years relevant industry experience
- Top level SoC architecture and associated IPs knowledge
- Experience with ARM architecture and leading silicon projects from concept to production
- Possess extraordinary leadership skills and ability to encourage and influence team members with a dedication to see the big picture
- Proven track record of managing sophisticated, multifaceted schedules, driving improvements and lessons learned into organizational and team processes and methodologies
- Working knowledge of software development processes and methodologies
- Current knowledge of pre-si modeling platforms (FPGA, simulation, emulation)
- Ability to build effective working relationships across multi-functional partners, engineers and management
- Excellent spoken and written communication skills with the ability to tailor communication style to multiple audiences
- Strong multi-tasking and real-time crisis leadership skills
- Ability to understand and extract action plans from sophisticated technical discussions and translate into succinct messaging for multifunctional and executive status reporting
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07.06.2025
A
Apple SoC Physical Design Verification Engineer United States, Oregon, Beaverton
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Minimum BS and 3+ years of relevant industry experience. Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology. Experience with ESD, macro placement design guidelines, digital/analog mixed...
Description:
In this highly visible role, you will be part of a critical team responsible for physical verification of an SOC.
- As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level.- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.- You will lead schedules and support cross-functional engineering efforts.- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
- Minimum BS and 3+ years of relevant industry experience.
- Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology.
- Experience with ESD, macro placement design guidelines, digital/analog mixed signal back-end verification checks and/or methodology.
- Knowledge of all aspects of ASIC physical design and physical verification checks.
- Scripting skills perl/python/tcl to debug flow related issues and automate checks.
- Experience with industry standard tools used for physical verification: Mentor Calibre, and/or Synopsys ICV.
- Tapeout experience with a track record of successful signoff.
- Layout design experience.
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Share
Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and/or Timing Closure. Programming skills with Perl and TCL. Hands-on experience in STA. Familiar with important...
Description:
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
- Minimum BS and 3+ years of relevant industry experience.
- Experience with large design STA and/or Timing Closure.
- Programming skills with Perl and TCL.
- Hands-on experience in STA.
- Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies.
- Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others.
- Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
- Familiar with ECO techniques and implementation.
- Good communicator who can accurately describe issues and follow them through to completion.
Show more
These jobs might be a good fit
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