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Soc Power/performance/thermal Engineering Program Manager jobs at Apple in United States, Beaverton
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United States
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Beaverton
32 jobs found
28.07.2025
A
Apple SoC Physical Design Engineer STA/Timing United States, Oregon, Beaverton
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Description:Full job details
Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and/or Timing Closure. Programming skills with Perl and TCL. Hands-on experience in STA. Familiar with important...
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29.06.2025
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Apple SoC Power Flow Methodology Engineer United States, Oregon, Beaverton
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A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience. Good understanding of VLSI designs and SOC design flows. Strong passion...
28.06.2025
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Apple CPU Performance Engineer United States, Oregon, Beaverton
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Minimum BS and 10+ years of relevant industry experience. Experience in CPU performance architecture, performance modeling, micro-architecture design, performance analysis. Experience with C and C++ and at least one of...
28.06.2025
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Apple SoC Physical Design Engineer STA/Timing United States, Oregon, Beaverton
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Description:Full job details
Minimum Bachelor's degree. Experience with STA. Experience with noise, crosstalk, and/or OCV effects. Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies. Experience with STA...
07.06.2025
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Apple CPU Debug Power Management Microarchitect/RTL Engineer United States, Oregon, Beaverton
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Minimum BS and 10+ years of relevant industry experience. Experience with Verilog or VHDL. Experience with simulators and waveform debugging tools. Experience with logic design with timing and power implications....
07.06.2025
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Apple SoC Silicon Debug Engineering Program Manager United States, Oregon, Beaverton
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SOC / VLSI Chip Design, Post Silicon Validation or Product Engineering experience. Post-silicon debug experience. Relevant technical program management, technical leadership or vendor management experience. BS and 3+ years relevant...
07.06.2025
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Apple SoC Physical Design Verification Engineer United States, Oregon, Beaverton
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Minimum BS and 3+ years of relevant industry experience. Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology. Experience with ESD, macro placement design guidelines, digital/analog mixed...
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Description:Full job details
Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and/or Timing Closure. Programming skills with Perl and TCL. Hands-on experience in STA. Familiar with important...
These jobs might be a good fit
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