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Apple SoC Physical Design Verification Engineer United States, Oregon, Beaverton 636142113
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In this highly visible role, you will be part of a critical team responsible for physical verification of an SOC.
- As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level.- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.- You will lead schedules and support cross-functional engineering efforts.- You will work on padring, bump, RDL design, and working with the package and floorplan teams.
- Minimum BS and 3+ years of relevant industry experience.
- Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology.
- Experience with ESD, macro placement design guidelines, digital/analog mixed signal back-end verification checks and/or methodology.
- Knowledge of all aspects of ASIC physical design and physical verification checks.
- Scripting skills perl/python/tcl to debug flow related issues and automate checks.
- Experience with industry standard tools used for physical verification: Mentor Calibre, and/or Synopsys ICV.
- Tapeout experience with a track record of successful signoff.
- Layout design experience.
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