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Apple CPU Debug Power Management Microarchitect/RTL Engineer United States, Oregon, Beaverton 569250100
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As a CPU Debug and Power Management Microarchitect/RTL Engineer, you will own or contribute to the following:• RTL ownership of CPU debug, trace, power management, clock management, and timer logic - development, assessment, and refinement of RTL design to target power, performance, area and timing goals• Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural features, develop micro-architectural details, and arrive at a detailed specification• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - Aid in debug of issues at SoC level related to CPU power management, clock control, and debug features. Work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
- Minimum BS and 10+ years of relevant industry experience
- Experience with Verilog or VHDL
- Experience with simulators and waveform debugging tools
- Experience with logic design with timing and power implications
- Knowledge and understanding of microprocessor architecture
- Expertise in one or more of the following areas: multiple clock/power domains and power management strategies, hardware debug and trace capabilities, DFT strategies, interrupt controllers, memory subsystem queuing, scheduling - starvation and deadlock avoidance, fabric communication protocols and interconnects
- SRAM design basics
- Understanding of low power microarchitecture techniques
- Understanding of high-performance design techniques and trade-offs
- Experience in C or C++ programming
- Experience using an interpretive language such as Python or Perl
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