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Apple CPU Silicon Timing Correlation Engineer India, Karnataka, Bengaluru 997851185
02.05.2024
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Key Qualifications
- Minimum BS and 10+ years of relevant industry experience
- Good all round hardware and data analysis skills
- Good understanding of VLSI design practice and static timing analysis
- Data analysis skills and experience using Python/JMP
- Understanding of SoC/CPU architecture is desirable
- Grasp of structural test (ATPG, MBIST) methods is highly desirable
- Proven ability to lead a broad team towards successful closure on timing debug issues
- Track record of innovation in the area of silicon timing correlation
- Lab experience (system, board or tester platform) required
- Excellent teamwork and communication. Ability to work with multiple teams in delivering a solution.
Description
- Create and refine methodologies for isolating and debugging timing failures in system and on tester- Develop, modify and deploy tests on silicon as part of characterization plan- Analyze silicon parametric data and correlate with empirical observations- Maintain and improve infrastructure for gathering silicon parametric data at scale- Enhance existing silicon debug features and conceive of new ones.
Education & Experience
Minimum BS and 10+ years of relevant industry experience
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