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Google RTL Design Engineer TPU Compute United States, California, Sunnyvale 994068965
22.07.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Experience with digital design using SystemVerilog RTL.
Preferred qualifications:
- 4 years of experience with post-graduate digital design using SystemVerilog RTL.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience applying computer architecture principles to solve open-ended problems.
- Knowledge of processor design, accelerators, or memory hierarchies.
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