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What you will be doing:
Learn and analyze system-level operation of NVIDIA DPUs
Debug and root-cause performance issues in pre-silicon environments, across RTL, waveform traces, and multi-die system simulations.
Collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
Develop and improve validation methodologies for performance experiments and data collection.
Automate repetitive debug and validation tasks to scale coverage and efficiency.
What we need to see:
B.Sc. in Electrical Engineering, Computer Engineering, or equivalent
3+ years of experience in ASICdevelopment/validation.
Strong background in ASIC debug, including reading RTL, analyzing waveforms, and root-causing functional or performance issues.
Hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems).
Proficiency with Python and C/C++ in a Linux environment.
Excellent interpersonal skills and ability to work optimally as part of a multi-functional team.
Ways to stand out from the crowd:
Shown expertise in performance modeling, traffic generation, or architecture studies.
Experience with modern interconnects and protocols (e.g., PCIe, Ethernet, CHI).
Familiarity with emulation platforms (e.g., Palladium, Veloce, FPGA prototyping).
Passion for experimental work, data-driven validation, and creative problem solving.
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