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As Senior DFT engineer, you will impact and see the device through its entire lifecycle, from definition stage to mass production. You will work in close collaboration with multiple VLSI engineering groups including chip design, verification, backend, test, reliability and more.To learn more about Annapurna Labs, you're welcome to watch the following videos from the recent re:Invent conference:Tel Aviv, ISR
- • Bachelor’s degree in Computer Engineering/Electrical Engineering
- • 2-4 years of experience with RTL and Gate Level Verification
- • Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification)
- • Verilog/SystemVerilog
- • Knowledge with Memory BIST and JTAG protocol .
- • Experience with Chip design
- • Scripting (Perl/Tc/Python)
- • Energetic, self-motivated
- • Pro-active, oriented on execution
- • Attentive to details and quality
- • Team player
- • Good communications and reporting skills
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