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Apple Wireless Design Verification Engineer United States, California, Cupertino 974731644
13.06.2024
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Description
This role will provide the opportunity to develop testbenches and create directed / constrained random tests, simulate, and debug. There will be regression triaging, along with analyzing coverage, improve flows and run RTL and gate-level functional simulations. You'll also work closely with the design teams to review specifications and architecture, extract features, define verification plan & coverage model
Key Qualifications
- Knowledge of ASIC verification simulation and testbench development flows with SystemVerilog and UVM
- Experience with constrained random testing, coverage closure, and RTL / gate simulations
- Experience with scripting in languages such as Python, Perl, Bash or similar
- Experience with communication / networking chips is a plus
- Phenomenal teammate with excellent communication skills and the desire to seek diverse challenges
Education & Experience
Bachelors required.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $55.82 and $84.09/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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