Western Digital Staff Engineer ASIC Development Engineering RTL FPGA Design 

Philippines, Baguio 

972530027

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

• Your main responsibilities as part of a winning group:

• Complex logic blocks & IPs design
• Work in a multi-disciplinary environment with a variety of complex interfaces.

Qualifications

• BSc in EE, CE, or equivalent
• 5-8 years of experience in RTL logic design
• Knowledge in synthesis and timing analysis
• Experience with FPGA - Advantage
• Experience & Knowledge with System Verilog - Strong Advantage
• Experience in multi clock and high frequencies designs - Advantage
• Deep knowledge of the following tools is an advantage: Vivado, NCSim, Synplify
• Knowledge simulation environment System Verilog based – advantage
• Experience in standard protocols such eMMC, UFS, USB, PCIe, and DDR4 – advantage
• Knowledge with Perl/python – advantage
• Experience in board design would be an added advantage
• Good communication and/or interaction skills among groups - local and abroad)
• Ability to communicate multiple interfaces inside the company
• Innovation capabilities
• Team worker