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What you will be doing:
You will own developing verification components like checkers, models, coverage, stimulus etc. Work closely with the Architecture, RTL and Formal verification teams to both understand the micro-architecture and also to ensure bug free RTL. Participate in Design specification reviews, architecture reviews, other unit and integrate testplan reviews.
Build DV code and Algorithms that are high quality with excellent time/space complexity, that scales well to higher testbenches.
You will actively work on understanding the ARM architecture, coherency protocols like CHI and the unit micro-architecture. Become an expert on the CPU load/store, MMU, caching,coherency/consistency,
What we need to see:
BS or MS in Electronics Engineering with 4+ years of experience
Good grasp of Design Verification Methodologies
SV/UVM or equivalent verification languages and methodologies.
Strong problem solving - more specifically DV code like stimulus, models, constraints, coverage.
Good grasp of typical Testbench architecture and Verification components
Strong Understanding of CPUArchitecture/computerorganisation and design, specifically understanding load/store, caching and coherency concepts is a plus.
Way to stand out from the crowd:
Understanding computer organization and design concepts related to load/store, caching, coherency, consistency and ordering
Previous experience in CPU Design verification.
Use of EDA tools from Synopsys or cadence.
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