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Apple SerDes Micro Architect United States, Oregon, Beaverton 962280130
28.03.2024
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Key Qualifications
- Experience leading the definition of high-speed SERDES receiver, transmitter, and clocking blocks
- Deep understanding of adaptation and optimization algorithms
- Deep understanding of communications and information theory
- Proficiency in equalizers, timing recovery and system identification
- Proficiency in DSP concepts and applications
- Familiarity with mixed-signal modeling in Python/MATLAB/C/C++
- Experience in system design and performance tradeoff
- Familiarity with simulation tools for analog, digital, and/ or mixed-signal circuits
- Familiarity with Machine Learning concepts
- Experience in firmware or embedded software development is a plus
Description
You will define the Micro Architecture of analog mixed-signal IPs with emphasis on SERDES design. You will review firmware code, analog and digital circuits and will verify that the design meets performance requirements. You will work with silicon evaluation and design verification teams to define expected behavior. You would lead the debug effort in system bring up and factory test. You will work with signal integrity engineers to determine system requirements.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
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