Nvidia Senior ASIC Clock Engineer 

Israel, North District 

948406328

is looking forexperienced top notchASIC design engineer to work on next generation of Nvidia Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. The complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality.locking design needs to balance high frequency clocks with power, DF, noise, circuit and physical design constraints.

be doing:

• Working on next generation of Networking Switch, NIC and SoC products.
• Micro architect and design next generation clock topologies and modules.
• ASIC Clock scheme definition.
• Improve Power, Performance, and Area (PPA) of state-of-the-art NVIDIAchips by evaluatingtrade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
• Collaborate withPhysical design and timing teamtoevaluateClockingconcernsand come up with solutions for supporting high speed Clocking.
• Understand physical aspects of the chip and developenhancedclock distribution techniques.
• Get involved in end-to-end cycle ofASICexecution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
• Support Post-Si debug, characterization and productization activities.

What we need to see:

• cor MScdegrees in EE orequivalent experiencefrom known universities.
• At least5+ years of work experiencein RTL design, Gate-Level and Circuit design optimization.
• Deep understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and ability tocollaboratewith multiple teams.
• Excellent problem solving and debugging skills.

Ways to stand out from the crowd:

• Prior experience in RTL design (Verilog), verification and synthesis.
• Clock IPs profound knowledge: PLL, DLL, Compensator.
• Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks.